| 研究生: |
林冠宏 Lin, Kuan-Hung |
|---|---|
| 論文名稱: |
用於H.264/AVC模式決策之近似平方預測法則及其VLSI實現 An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation |
| 指導教授: |
劉濱達
Liu, Bin-Da 楊家輝 Yang, Jar-Ferr |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2008 |
| 畢業學年度: | 96 |
| 語文別: | 英文 |
| 論文頁數: | 77 |
| 中文關鍵詞: | 預測 、近似平方 |
| 外文關鍵詞: | intra prediction, H.264, approximate square |
| 相關次數: | 點閱:140 下載:2 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文中,我們實現一個適用於H.264/AVC模式決策之近似平方預測法則及其硬體。在時域的計算之下,普遍採用的預測的方式有SAD(sum of absolute difference)與SSD(sum of square difference)兩種。比起SAD,由於SSD使用到平方器,因而可得到較好的影像品質,但相對的卻增加許多計算複雜度而降低硬體效能。為了能加速H.264/AVC的內框預測,我們利用一個偵測器來決定移位的多寡,只需將偵測的值經過移位器即可得到最後結果。如此,相較於平方器,面積與運算速度可得到大幅的改善。
在模擬的數據中,我們可以得知提出的方法有效地提升硬體的速度,並且僅伴隨著非常微小影像品質的降低。在硬體架構方面,總共需要31,228個邏輯閘,在佈局的實現上,總共的面積為435,786 μm2。當我們針對一個巨大區塊(macroblock)做預測時,總共需要1078個時脈週期數。在採用SASD的計算方式下,內框預測架構可以達到的最大操作頻率為133 MHz,比起SSD的計算方式可以增加約33%的速度。此方法可以即時地針對720p HD (1280×720)影像大小成功地實現預測的過程,並且此時的影像頻率是以每秒30張畫面。
In this thesis, we propose an approximate square prediction criterion for H.264/AVC mode decision. Sum of absolute difference (SAD) and sum of squared difference (SSD) are two popular prediction criteria in the spatial domain. SSD achieves better video quality than SAD due to the square computation. The square operations take high computational complexity and large hardware cost. An efficient mode decision criterion is proposed to maintain the video quality compared to SSD. The proposed criterion much reduces the computational complexity and improves hardware performance by using a first-one-detector and shifter.
Simulation results show the total number of logic gates is 31.2k, and the core size of layout is 435,786 μm2. The proposed intra prediction architecture takes 1,078 clock cycles to predict one macroblock. The proposed architecture using the SASD criterion reduces more than 30% critical time delay compared with that using SSD. The maximum operation frequency is 133 MHz. For the real-time requirement, the maximum frame size achieves 720p HD (1280×720)@30 frames/sec while the sequence format is 4:2:0.
[1] Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbit/s – Part2: Video, ISO/IEC 11172, 1993.
[2] Information Technology – Generic Coding of Moving Pictures and Associated Audio Information: Video, ISO/IEC 13818-2 and ITU-T Rec. H.262, 1996.
[3] Information Technology – Coding of Audio-Visual Objects – Part2: Visual, ISO/IEC 14496-2, 1999.
[4] Video Codec for Audiovisual Services at px64 kbits/s, ITU-T Rec. H.261 v1, 1990.
[5] Video Coding for Low Bit Rate Communication, ITU-T Rec. H.263, 1998.
[6] Joint Video Team, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC, May 2003.
[7] V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures. Boston, MA: Kluwer Academic, 1997.
[8] Y. W. Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, “Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder,” IEEE Trans. Circuits Syst. Video Technol., vol. 15, pp. 378-401, Mar. 2005.
[9] J. C. Wang, J. F. Wang, J. F. Yang, and J. T. Chen, “A fast mode decision algorithm and its VLSI design for H.264/AVC intra-prediction,” IEEE Trans. Circuits Syst. Video Technol., vol. 17, pp. 1414-1422, Oct. 2007.
[10] W. C. Tsai, B. D. Liu and J. F. Yang, “Discrete cross difference mode detection for fast H.264 intra prediction,” Master thesis, National Cheng Kung University, Tainan, Taiwan, July 2007.
[11] F. Pan, X. Lin, S. Rahardja, K. P. Lim, Z. G. Li, D. Wu, and S. Wu, “Fast mode decision algorithm for intra prediction in H.264/AVC video coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 15, pp. 813-822, July 2005.
[12] A. C. Tsai, A. Paul, J. C. Wang, and J. F. Wang, “Intensity gradient technique for efficient intra-prediction in H.264/AVC,” IEEE Trans. Circuits Syst. Video Technol., vol. 18, pp. 694-698, May 2008.
[13] H. Li, K. N. Ngan, and Z. Wei, “Fast and efficient method for block edge classification and its application in H.264/AVC video coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 18, pp. 756-768, Jun. 2008.
[14] B. Meng, O. C. Au, C. W. Wong, and H. K. Lam, “Efficient intra-prediction mode selection for 4×4 blocks in H.264,” in Proc. IEEE ICME, July 2003, pp. 521-524.
[15] Y. N. Sairam, N. Ma, and N. Sinha, “A novel partial prediction algorithm for fast 4×4 intra prediction mode decision in H.264/AVC,” in Proc. IEEE DCC, March 2008, pp. 232-241.
[16] S. Vassiliadjs, E. A. Hakkennes, J. S. S. M. Wong, and G. G. Pechanek, “The sum-absolute-difference motion estimation accelerator,” in Proc. Euromicro Conf., Aug. 1998, pp. 559-566.
[17] D. Guevorkian, A. Launiainen, P. Liuha, and V. Lappalainen, “Architectures for the sum of absolute differences operation,” in Proc. IEEE SIPS, Oct. 2002, pp. 57-62.
[18] J. Vanne, E. Aho, T. D. Hamalainen, and K. Kuusilinna, “A high-performance sum of absolute difference implementation for motion estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, pp. 876-883, July 2006.
[19] J. T. Yoo, K. F. Smith, G. Gopalakrishnan, “A fast parallel squarer based on divide-and-conquer,” IEEE J. Solid-State Circuits, vol. 32, pp. 909-912, June 1997.
[20] G. Sullivan, T. Wiegand, and K. P. Lim, “Joint model reference encoding methods and decoding concealment methods,” presented at the 9th JVT Meeting (JVT-I049d0), San Diego, CA, Sept. 2003.
[21] C. H. Tseng, H. M. Wang, and J. F. Yang, “Enhanced intra-44 mode decision for H.264/AVC coders,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, pp. 1027-1032, Aug. 2006.
[22] L. M. Po and K. Guo, “Transform-domain fast sum of the squared difference computation for H.264/AVC rate-distortion optimization,” IEEE Trans. Circuits Syst. Video Technol., vol. 17, pp. 765-773, June 2007.
[23] Joint Video Team, H.264/AVC Reference Software, version 12.3, Aug. 2007. [Online]. Available: http://iphome.hhi.de/suehring/tml/download/
[24] Y. W. Huang, B. Y. Hsieh, T. C. Chien, and L. G. Chen, “Hardware architecture design for H.264/AVC intra frame coder,” in Proc. IEEE ISCAS, May 2004, pp. 269-272.
[25] E. Sahin and I. Hamzaoglu, “An efficient hardware architecture for H.264 intra prediction algorithm,” in Proc. IEEE DATE, Apr. 2007, pp. 1-6.
[26] E. Sahin and I. Hamzaoglu, “An efficient intra prediction hardware architecture for H.264 video decoding,” in Proc. IEEE DSD, Aug. 2007, pp. 448-454.
[27] S. B. Wang, X. L. Zhang, and Z. Wang, “H.264 intra prediction architecture optimization,” in Proc. IEEE ICME, July 2007, pp. 1571-1574.
[28] C. W. Ku, C. C. Cheng, G. S. Yu, M. C. Tsai, and T. S. Chang, “A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, pp. 917-928, Aug. 2006.
[29] K. Suh, S. Park, and H. Cho, “An efficient hardware architecture of intra prediction and TQ/IQIT module for H.264 encoder,” ETRI Journal, vol. 27, pp. 511-524, Oct. 2005.
[30] C. H. Tsai, Y. W. Huang, and L. G. Chen, “Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction,” in Proc. IEEE MWSCAS, Aug. 2005, pp. 47-50.