| 研究生: |
劉忠瑋 Liu, Chung-Wei |
|---|---|
| 論文名稱: |
具快速負載暫態之背景式校正電容電流偵測四相降壓轉換器 A Four-Phase Buck Converter with Background-Calibrated Capacitor-Current Sensor for Fast Load-Transient Application |
| 指導教授: |
郭泰豪
Kuo, Tai-Haur |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2019 |
| 畢業學年度: | 107 |
| 語文別: | 英文 |
| 論文頁數: | 86 |
| 中文關鍵詞: | 直流-直流降壓轉換器 、快速負載暫態響應 、背景式電容電流偵測器校正 、多相式降壓轉換器 |
| 外文關鍵詞: | DC-DC buck converter, fast load-transient response, background capacitor current sensor calibration, multiphase buck converter |
| 相關次數: | 點閱:131 下載:7 |
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本論文提出一個可操作於固定頻率下背景式校正之電容電流偵測器。在先前的校正技術中,針對輸出電容的容值和其寄生電阻的阻值、寄生電感的感值進行校準過程時將改變切換頻率,以呈現輸出阻抗的特性。但是,由於變動至較低頻率時,將增大輸出電壓漣波。因此,本論文提出了一種在固定切換頻率下即可校正電容電流偵測器的方法,使得降壓轉換器在進行背景式校正或正常操作時,都可以使輸出電壓漣波滿足預期規格。
在前作中,電容電流偵測器僅限在輕載條件下進行校準。本作提出可在輕載和重載條件下執行背景式電容電流偵測器校正,以提高電容電流偵測器校準的靈活性。此外,為了減少因相位數轉換造成的電壓抖動,本作使用了相關的輔助電路,使轉換器得以在不同相位的情況下進行平順的切換。
本作將上述技術實現於TSMC 0.18μm 互補型金氧半導體製程,晶片面積為2.538 mm2。量測結果顯示,在負載電流為2安培 / 5奈秒 的步階抽載下,VO下衝/過衝和安置時間為分別為33毫伏 / 48毫伏及48奈秒 / 55奈秒。在1安培負載電流下進入背景式校正時,相位轉換引起的輸出電壓下衝/過衝為30毫伏和5毫伏。
In this thesis, a background capacitor-current sensor (CCS) calibration with fixed frequency operation is proposed. In previous works, the procedure of the calibration for output capacitance (CO), parasitic resistance on CO (RESR), and parasitic inductance on CO (LESL) will change the switching frequency to present the characteristics of the output impedance (ZCo). However, the output voltage ripple will be enlarged caused by the lower frequency. Thus, this work proposes a method to calibrate CCS under fixed switching frequency, which can let output voltage ripple to meet the target specification no matter when during background calibration or normal operation.
The scenario of CCS calibration in previous works is limited to operate only under light load condition. To increase the flexibility of CCS calibration, this work can execute background CCS calibration under light load and heavy load condition. In addition, some auxiliary circuits are implemented in this work to achieve smooth transition of different phase counts, reducing the fluctuation of output voltage.
These proposed techniques are implemented in TSMC 0.18μm CMOS process with a chip area of 2.538 mm2. Measurement results shows that the VO undershoot/overshoot and settling time are 33mV / 48mV and 48ns / 55 ns of a load-current step of 2A/5ns. The VO undershoot/overshoot caused by phase transition when entering background calibration under 1A load current are 30mV and 5mV.
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