隨著物聯網發展，對於嵌入式系統的功耗與效能要求益趨提高，隨著系統複雜度的上昇，也讓系統的設計難度明顯增加。而在以微控制器為核心的嵌入式系統中，快取記憶體的配置直接影響著系統效能與功耗。另外內部通訊架構的複雜化，使得其所佔的功耗越來越無法被忽略，而其與快取資料存取路徑上的關係，使其也影響著快取記憶體配置上的選擇，然而近幾年的快取記憶體探勘的相關研究，大部份只考慮到快取本身與下一級記憶體，在未考量通訊架構上的延遲與功耗的情況下，將使得整體節能效益無法更進一步的改進。

本論文提出一針對具匯流排之嵌入式系統於快取配置探勘之虛擬平台，而此平台是以電子系統層級的概念建置而成，其具備有在同時考量軟體運行與匯流排架構的影響下，對快取記憶體的配置與其於系統上的位置作快速效能與耗能分析之能力，進而幫助整體系統設計之優化。

With the development of Internet of Things (IoT), the power consumption and performance requirements of the embedded system increases as the system complexity rises. In the same time, the design challenge of the system is obviously raised, too. In the embedded system with a microcontroller, the configuration of the cache memory directly affects the system performance and power consumption. In addition, the complexity of the internal communication architecture makes its power consumption significantly increase. Its relationship with the cache access path also affects the choice of the cache memory configuration. However, in recent years, most studies of cache memory exploration only considers the cache itself, not consider the delay and power consumption of the communications architecture. This will limit the improvement of the overall energy efficiency.

In this paper, we propose a virtual platform for cache configuration and location exploration on a bus-based embedded system. The platform is established based on the concept of the Electronic System Level. It has ability to consider the effect of application and the bus architecture, and is able to do fast performance and power estimation to configuration of cache memory and its position on the system, and thus help designers to optimize energy efficiency of the overall system.

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