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研究生：	劉湘偉 Liu, Hsiang-Wei
論文名稱：	以切換式運算放大器為基礎之一伏特十位元管線式類比數位轉換器 A 1-V 10-Bit Pipelined A/D Converter Based on Switched-Opamp Technique
指導教授：	劉濱達 Liu, Bin-Da
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	92
中文關鍵詞：	類比數位轉換器、管線式、切換式運算放大器
外文關鍵詞：	analog-to-digital converter, switched-opamp, pipelined
相關次數：	點閱：71 下載：5
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　　隨著製程技術的演進和可攜式消費型產品的普及，具有低電壓和低功率消耗能力的積體電路已經變成在積體電路設計上的主流和挑戰。當供應電壓開始降低的時候，會減少電路中信號的動態範圍，而且在管線式類比數位轉換器中，最為主要的構成要素為切換電容電路，然而切換電容電路在低供應電壓的條件下，浮動開關卻會變成主要的障礙。
　　本論文中，使用可以提供具有可靠性解決方案的切換式運算放大器技術，使得電路可以不需要特殊製程和增加時脈訊號電壓的電路，正常地操作在低供應電壓條件之下。一個可切換的差動運算放大器具有兩組輸出信號對，是採用兩階的電路架構方式設計；而在類比數位轉換器的前端取樣和保留電路，使用額外的附加有可以提高時脈控制訊號電壓電路的開關，來擷取輸入訊號；具有放大倍率的數位類比轉換器使用切換式運算放大器電路和額外的電容分支電路來完成於低電壓的操作。
　　使用每階可處理1.5位元架構的管線化類比數位轉換器，在台積電 0.18 微米一層多晶矽六層金屬之互補式金氧半製程中，其組成的各子電路以及整個類比數位轉換器的系統，在一伏特的供應電壓的條件之下被設計且經由模擬完成驗證。在輸入訊號頻率為 35.4 千赫茲以及取樣頻率為 2.5 百萬赫茲時，管線式類比數位轉換器的訊號對於雜訊及諧波失真比為 56.195 dB，而微分非線性誤差在 ±0.8 LSB 的範圍，積分非線性誤差在 ±1.6 LSB 的範圍，整個電路的功率消耗為 65.85 mW。

　　With the evolution of process technology and the prevalence of the portable consuming products, low-voltage and low-power capabilities have become the mainstream and challenge of integrated circuit design. As the supply voltage scales down, the dynamic range is reduced and the floating switch becomes a major obstacle in most switched capacitor based circuit, which is the primary constitutive component in pipelined ADC design.
　　In this thesis, switched-opamp technique provides a reliable scheme to achieve low-voltage operation without special processes or boosted clock voltage. The differential switchable opamp is designed in a two-stage fashion whereas with dual outputs pairs. The S/H fetches the input by using additional bootstrapped switches at the front end of ADC. The MDAC applies the switched-opamp technique as well as extra capacitor branches to achieve low voltage operation.
　　A 1.5-bit/stage of pipelined ADC with 1-V supply voltage is designed. The subcircuits and whole system design have been verified using the TSMC 0.18 μm 1P6M CMOS process. The SNDR of the pipelined A/D converter is 56.195 dB with sampling frequency of 2.5 MHz and input frequency of 35.4 kHz. The DNL ranges between ±0.8 LSB and the INL ranges between ±1.6 LSB. The total power consumption is 65.85 mW.

Table of Contents...i	
Acknowledgement...iv	
Abstract...v	
Figure Captions...vii
Table Captions...xii

Chapter 1 Introduction...1	
1  Motivations...1	
2  Thesis Organization...3
	
Chapter 2 Fundamentals of A/D Converter...5
1  Introduction...5
2  Basic Concepts...6	
2.1 Introduction to Analog-to-Digital Converters...6
2.2 Ideal A/D Converter...8
2.3 Quantization Noise...10
3  Specifications...12
3.1 Static specifications...12
3.2 Dynamic specifications...15
4  Classification...18
5  High-Speed A/D Converter Architectures...19	
5.1 Flash A/D Converter...19	
5.2 Two-Step A/D Converter...20	
5.3 Folding and Interpolating A/D Converter...21	
5.4 Pipelined A/D Converter...25	
6  1.5-Bit/Stage Pipelined ADC and Digital Error Correction...27

Chapter 3 Low-Voltage Switched-Capacitor Circuit Technique...34
1  Introduction...34	
2  Floating Switch Problem at Low Supply Voltage...35	
3  Low-Voltage Switched-Capacitor Techniques...39	
3.1 Multi-Threshold MOSFET...39	
3.2 Clock Voltage Multiplier...40	
3.3 Bootstrapped Switch...41	
4  Principle of Switched-Opamp Technique...43	
5  Design Methodology of Switched Opamp...45	

Chapter 4 Building Block Design and Simulation Results...49	
1  Introduction...49	
2  Low-Voltage Sample-and-Hold Circuit...50	
2.1 Implementation of Bootstrapped Switch...52	
2.2 Simulation Results of Sample-and-Hold Circuit...54	
3  Low-Voltage Multiplying Digital-to-Analog Converter...56	
3.1 Conventional MDAC of 1.5-Bit / Stage Pipelined Architecture...57	
3.2 Low-Voltage MDAC...58	
4  Switched Opamp and Common Mode Feedback Circuit...62	
4.1 Specifications of Switched Opamp...63	
4.2 Low-Voltage Switched Opamp...66	
4.3 Common-Mode Feedback Circuit...68	
4.4 Simulation Results of Switched Opamp...70	
5  Low-Voltage Comparator and Sub-ADC...73	
5.1 Low-Voltage Comparator...73	
5.2 Sub-ADC...77	
6  Clock Generator...79	
7  Simulation Results of Low-Voltage Pipelined A/D Converter...81	
8  Summary...85	

Chapter 5 Conclusions and Future Work...86	
1  Conclusions...86	
2  Future Work...87	
References...88
                                    

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校內：2006-07-14公開
校外：2007-07-14公開

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