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研究生：	羅世明 Luo, Shih-Ming
論文名稱：	具多重解析度之內建自我抖動測試電路的設計與實現 Design and Implementation of a Multi-resolution Built-In Self-Test Circuit for Jitter Measurement
指導教授：	張順志 Chang, Soon-Jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	55
中文關鍵詞：	內建自我測試、抖動量測、時間轉數位碼電路、脈波放大器、多重解析度
外文關鍵詞：	BIST, TDC, jitter measurement, pulse amplifier, multi-resolution
相關次數：	點閱：124 下載：2
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在本論文中，我們針對近年來量測時脈抖動的內建自我測試技術進行研究及探討，並歸納出應用於量測訊號抖動內建自我測試電路之各種方法的優點與可能面臨的挑戰。
不同於傳統上基於一個理想訊號來實現內建自我測試的方法，本論文提出一個不需理想參考訊號之自我參考訊號技術，在所提出的抖動自我量測電路中包含兩個主要的子電路：脈波放大器(Pulse Amplifier)與以環型振盪器為基礎的時間轉數位碼電路。脈波放大器主要用來將待測訊號的時間差異線性放大以等效提高量測解析度。於本論文，我們使用了三種不同的放大倍率(1倍/2.5倍/6倍)來調整抖動自我量測的解析度，因此，電路擁有多重解析度(65 ps/26 ps/11 ps)，以滿足不同頻率下的抖動量測範圍；而以環型振盪器為基礎的時間轉數位碼電路用以建立訊號抖動的機率分佈長條圖(Histogram)，再透過統計分析的技巧對量測結果進行校正，以得到較高的準確性。
所提出的電路設計是使用TSMC 0.18 m 1P6M的製程，且量測頻率範圍為65 MHz ~ 909 MHz。電路所佔用的面積為0.7225 mm2，而電源為1.8 V的消耗功率是9 mW。

In this thesis, we survey and investigate the recent built-in self-test (BIST) schemes for jitter measurement. We also summarize advantages, drawbacks and challenges in the implementation of these BIST schemes.
A reference-free technique is applied to the proposed BIST to eliminate the need of tunable delay in conventional jitter-free reference BIST circuit. The proposed BIST circuit for jitter measurement mainly contains two building blocks: a pulse amplifier and a ring oscillator based time-to-digital converter (TDC). A pulse amplifier is used to linearly amplify the time intervals of signal under test (SUT) to enhance the measuring resolution. We design three gains (1 times/2.5 times/6 times) of the pulse amplifier to adjust resolution in the proposed BIST circuit for jitter measurement. So, the BIST circuit has three values of resolution functions (11 ps/26 ps/65 ps) to optimize the measurement time and measurement range when we have to measure different jitter quantities. The ring oscillator based TDC transfers the timing period to digital outputs and then the histogram of jitter is built to estimate the amount of jitter.
The proposed circuit is designed in TSMC 0.18 m 1P6M process, and the measured frequency is from 65 MHz to 909 MHz. The chip occupies a silicon area of 0.7225 mm2. The total power consumption is 9 mW from a 1.8 V supply voltage.

Abstract.................................................................................iii
Acknowledgement.................................................................v
Table of Contents.................................................................vii
List of Figures........................................................................x
List of Tables........................................................................xii
================================================
Chapter 1 Introduction..........................................................1
1 Motivation.....................................................................1
2 Thesis Organization.......................................................3
Chapter 2 Basics for Jitter Measurement...............................4
1 Concepts of Jitter...........................................................4
1.1 Jitter and Phase noise................................................5
2 Jitter Classifications.......................................................6
2.1 Classified by Properties.............................................6
2.2 Classified by Measuring Time...................................7
3 Jitter Measurement.......................................................11
3.1 Jitter Statistics..........................................................11
3.2 Modeling Methods...................................................13
Chapter 3 Jitter Measurement and BIST Technologies........14
1 Equipment Based Techniques......................................14
2 BIST for Jitter Measurement Properties........................15
3 BIST for Jitter Measurement Circuits...........................17
3.1 The Delay line based TDC.......................................17
3.2 An ADC Based TDC [17]........................................23
Chapter 4 The Proposed BIST Circuit for Jitter             
             Measurement...............................................................26
1 The Structure of BIST circuit.......................................26
2 Reference-free Technique...........................................28
3 Signal Detector............................................................29
3.1 The Structure of Signal Detector..............................29
3.2 The Operation of Signal Detector............................30
4 Pulse Amplifier...........................................................30
4.1 The Structure of Pulse Amplifier.............................31
4.2 The Operation of Pulse Amplifier............................32
4.3 The Design of Pulse Amplifier................................32
4.4 The Simulation of Pulse Amplifier..........................33
5 Edge Detector.............................................................35
6 Ring Oscillator Based TDC.........................................35
6.1 VDL Based TDC v.s. Ring OSC. Based TDC.........36
6.2 The Structure of Ring Oscillator Based TDC..........37
6.3 The Operation of Ring Oscillator Based TDC.........38
6.4 The Design of Ring Oscillator Based TDC..............39
6.5 The Simulation of Ring Oscillator Based TDC........39
7 Multi-Resolution BIST Circuit.....................................41
Chapter 5 Layout and Simulation Results...........................42
1 Simulation of The Proposed BIST Circuit...................43
2 Layout of Proposed Jitter BIST Circuit.......................47
3 Comparison with Previous Work................................48
4 Test Setup...................................................................49
Chapter 6 Conclusions and Future work.............................50
1 Conclusions................................................................50
2 Future Work................................................................51
Reference...........................................................................52
                                    

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校內：2012-08-28公開
校外：2013-08-28公開

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