隨著製程進步，電晶體密度上升導致了積體電路的功率密度亦大幅上升。而功率密度的上升將使得晶片溫度升高，進而造成晶片功能失常或效率下降。同時，3D IC的結構更容易造成「熱點」而導致上述問題。如今，晶片架構的探索以及功率最佳化的研究常在電子系統層級平台上進行。上述研究對於晶片溫度的影響，便需要在平台上進行溫度模擬才能探究。
暫態分析可以求得各時間點晶片的溫度分布，然而此種分析常消耗大量時間與運算資源。為了減少模擬時間，本論文考慮應用三維不連續伽遼金法於晶片溫度暫態分析，提出了不連續伽遼金法於三維溫度分析之簡化公式，並具有平行運算特性的溫度分析方法與分析流程。和最先進的暫態分析方法相比，其運算速度達到2.77倍且誤差幅度為2.03%。

The density of transistors increase leads to the increase of power density of an integrated circuits. The increase of power density may lead to higher temperature that may, subsequently, result in higher chances of function failure or degradation of performance of a chip. Also, the structure of state-of-the-art three-dimensional stack ICs is much easier to cause “hot spots” and leads to the mentioned problems. Nowadays, the exploration of chip architecture and system-level power optimization can be performed at electronic-system-level platform to resolve heat issues. Hence, a fast and effective thermal analysis is needed to understand the temperature impact caused by various exploring architectures.

Transient thermal analysis can obtain distribution of temperatures on a chip at any specific time, however, the analysis is time consuming and resource hungry. To improve the simulation time, the three-dimensional discontinuous Galerkin method for heat equations is considered. In the thesis, we propose to simplify the discontinuous Galerkin method and provide high-level of parallelism features to speed up thermal analysis. When compared to the results obtained from the state-of-the-art transient thermal analysis, the proposed method can speed up by 2.77 times with marginal error by 2.03%.

[1] G.Van derPlas et al., “Design Issues and Considerations for Low-Cost 3-D TSV IC Technology,” IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 293–307, Jan.2011.
[2] W.Huang, S.Ghosh, S.Velusamy, K.Sankaranarayanan, K.Skadron, and M. R.Stan, “HotSpot: A compact thermal modeling methodology for early-stage VLSI design,” IEEE Trans. Very Large Scale Integr. Syst., vol. 14, no. 5, pp. 501–513, 2006.
[3] M.Pedram and S.Nazarian, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods,” Proc. IEEE, vol. 94, no. 8, pp. 1487–1501, 2006.
[4] B. J.Kane and T. T.Results, “Thermal Analysis Integrated in the IC Design Flow,” no. June, pp. 33–35, 2008.
[5] L.-Y.Lu and L.-Y.Chiou, “Temperature gradient-aware thermal simulator for three-dimensional integrated circuits,” IET Comput. Digit. Tech., vol. 11, no. 5, pp. 190–196, 2017.
[6] J.Fourier, Théorie analytique de la chaleur. Paris: Firmin Didot, 1822.
[7] J. R.Cannon and F. E.Browder, The One-Dimensional Heat Equation. Cambridge: Cambridge University Press, 1984.
[8] L. M.Jiji, Heat Convection. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009.
[9] T. I.Zohdi, A Finite Element Primer for Beginners. Cham: Springer International Publishing, 2015.
[10] J.-P.Berrut and L. N.Trefethen, “Barycentric Lagrange Interpolation,” SIAM Rev., vol. 46, no. 3, pp. 501–517, Jan.2004.
[11] B. Q.Li, Discontinuous Finite Elements in Fluid Dynamics and Heat Transfer. London: Springer-Verlag, 2006.
[12] J. S.Hesthaven and T.Warburton, Nodal Discontinuous Galerkin Methods, vol. 54. New York, NY: Springer New York, 2008.
[13] U. M. (Uri M. .Ascher andL. R.Petzold, Computer methods for ordinary differential equations and differential-algebraic equations. Philadelphia: Society for Industrial and Applied Mathematics, 1998.
[14] R.Qin and L.Krivodonova, “A discontinuous Galerkin method for solutions of the Euler equations on Cartesian grids with embedded geometries,” J. Comput. Sci., vol. 4, no. 1–2, pp. 24–35, 2013.
[15] W.Jia, B. T.Helenbrook, and M. C.Cheng, “Fast thermal simulation of FinFET circuits based on a multiblock reduced-order model,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 35, no. 7, pp. 1114–1124, 2016.
[16] R.Pinnau, “Model Reduction via Proper Orthogonal Decomposition,” Springer, Berlin, Heidelberg, 2008, pp. 95–109.
[17] K.Skadron, M. R.Stan, W.Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, and D.Tarjan, “Temperature-aware microarchitecture,” 30th Annu. Int. Symp. Comput. Archit. 2003. Proceedings., pp. 2–13, 2003.
[18] L. Y.Lu et al., “A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling,” Proc. Asia South Pacific Des. Autom. Conf. ASP-DAC, vol. 25-28-Janu, pp. 17–18, 2016.
[19] H. C.Hsieh, P. H.Huang, C. H.Lin, and H. L.Lin, “Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC,” Int. Syst. Chip Conf., pp. 317–321, 2012.