| 研究生: |
曾瑞鉉 Tzeng, Ruei-Shiuan |
|---|---|
| 論文名稱: |
運用三角調變器之內建式自我測試電路於類比數位轉換器 A Sigma-Delta Modulation Based BIST for A/D Converter |
| 指導教授: |
李昆忠
Lee, Kuen-Jong |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2002 |
| 畢業學年度: | 90 |
| 語文別: | 英文 |
| 論文頁數: | 77 |
| 中文關鍵詞: | 類比數位轉換器之內建式自我測試 、類比電路測試 、測試 、類比數位轉換器 、內建式自我測試 |
| 外文關鍵詞: | testing, BIST, ADC BIST, ADC, analog circuit testing |
| 相關次數: | 點閱:89 下載:3 |
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本論文中提出了兩個內建式自我測試策略,應用於量測類比數位轉換器之四個主要測試參數,即偏移誤差(Offset Error)、倍率誤差(Gain Error)、整體非線性誤差(Integral Nonlinearity Error)及差分非線性誤差(Differential Nonlinearity Error)。第一個測試策略可應用於測試單晶片系統內部的類比數位轉換器。以三角調變器為基礎設計一個內建式弦波信號產生器,以產生類比和數位弦波信號,藉由此類比和數位弦波信號,由弦波統計方式以近似方程式求得待測參數。此一架構具有下列優點:1) 可量測各頻率之參數; 2) 測試精準度高; 3) 可作動態弦波測試; 4) 晶片面積需求小。第二個測試策略應用於獨立之類比數位轉換器。利用類比濾波器之相位差和統計各量測的數位碼是否介於容許範圍內,判斷待測電路參數是否正確。此一架構具有下列優點:1) 可量測各頻率之參數; 2) 測試精準度高; 3) 可利用動態弦波進行測試; 4) 架構易於設計與實現。
我們以八位元類比數位轉換器為例,在TSMC 0.35μm 1P4M製程下針對上述兩項測試策略架構進行設計,經由Verilog-XL、Matlab與Simulink軟體模擬及驗証可以得知本論文所提出的測試策略其精確度可達到0.05 LSB。
In this thesis, two built-in self test (BIST) methodologies have been developed to measure the four parameters of the A/D converters: offset error, gain error, integral nonlinearity error, and differential nonlinearity error. The first methodology can be used to test the A/D converter in a system-on-a-chip (SOC). A sigma-delta modulation based signal generator is designed to concurrently produce analog and digital sinusoidal signals on chip. By the sinusoidal histogram technique, the parameters can be extracted by the approximated equations. This structure has the following advantages: 1) parameter measurement capability for different frequencies; 2) high accuracy; 3) dynamic sinusoidal testing capability; 4) low chip area overhead. The second methodology is used to test the stand-alone A/D converters. By utilizing the phase delay of the analog filter and statistic measured codes, whether the device under test is correct or not can be determined. This structure has the following advantages: 1) parameter measurement capability for different frequencies; 2) high accuracy; 3) dynamic sinusoidal testing capability; 4) easy to design and implement.
The proposed structures are designed and simulated in an 8-bit A/D converter by using the TSMC 0.35μm 1P4M technology. With the Verilog-XL, Matlab, and Simulink tools, it is shown that the accuracy of offset error test, gain error test, integral nonlinearity error test, and differential nonlinearity error test are all less than 0.05 LSB.
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