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研究生：	汪逸青 Wang, Yi-Cing
論文名稱：	具有同步整流之多輸出串接式半橋轉換器研製 Design and Implementation of Multi-output Cascaded Half-bridge Converter with Synchronous Rectification
指導教授：	楊宏澤 Yang, Hong-Tzer
共同指導教授:	李嘉猷 Lee, Jia-You
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	99
語文別：	英文
論文頁數：	66
中文關鍵詞：	串接式轉換器、同步整流
外文關鍵詞：	Cascaded converter, synchronous rectification
相關次數：	點閱：76 下載：3
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為符合通訊與電腦電源產品多輸出和低電壓應力需求特性，對稱式半橋架構適用於直流對直流電源轉換應用。本論文旨在提出一具有同步整流之多輸出串接式半橋轉換器。所提主電路前級轉換器操作在開迴路，經整流以後提供一接近直流電壓作為後級轉換器輸入電壓，而後級為閉迴路控制以達到輸出穩壓目的。於後級迴授設計為單獨控制迴路，因此每個模組輸出不會互相影響，故可簡化擴充多輸出之穩壓控制。另為減少輸出整流二極體的導通損失，因此使用同步整流技術取代整流二極體。所研製轉換器規格為輸出功率為240瓦、切換頻率50k赫茲，具雙輸出的電路雛型，本文經實驗結果驗證所提電路設計與實作的可行性。

For requirements of multi-output and low voltage stress on power devices by telecom or PC power products, symmetrical half-bridge converter (SHBC) is considered suitable for DC/DC power conversion applications. The purpose of this thesis is to design and implement a multi-output half-bridge converter with synchronous rectification. The converter consists of two stages. The front-end stage operates at open-loop condition to transfer its DC output voltage as the input of the back-end stage. The back-end stage is designed to have several independent modules in parallel with each module cross regulated. Constant-voltage output requirements of the regulated multiple-outputs can thus be met. Moreover, in order to reduce the conduction loss caused by the diode, synchronous rectifier is adopted to replace the original diode rectifier. To demonstrate its feasibility, the proposed topology has been implemented on a 240W, 50 kHz, and dual-output prototype converter. Simulated and experimental results are presented to verify the performance of the proposed circuitry.

摘要 IV
Abstract V
誌 謝 VI
TABLE OF CONTENTS VII
LIST OF TABLES	XI
LIST OF FIGURES	XII
Chapter 1 Introduction	1
1 Backgrounds	1
2 Motivation	5
3 Contributions of the Thesis	6
4 Thesis Organization	7
Chapter 2 Review on Existing Circuits 8
1 Introduction 8
2 Buck DC-DC Converter with synchronous rectification	9
2.1 Circuit Description 9
2.2 Assumptions 9
2.3 Circuit analysis for time interval 0 < t < DT 10
2.4 Circuit analysis for time interval DT＜t < T 11
2.5 DC voltage transfer function for CCM 12
3 Boost DC-DC Converter with synchronous rectification 14
3.1 Circuit Description 14
3.2 Assumptions 14
3.3 Circuit analysis for time interval 0 < t < DT 14
3.4 Circuit analysis for time interval DT < t < T 16
3.5 DC transfer function for CCM 17
4 Symmetrical Half–bridge DC-DC converter with synchronous  rectification 19
4.1 Circuit Description 19
4.2 Assumptions 19
4.3 Circuit analysis for time interval 0 < t < DT 20
4.4 Circuit analysis for time interval DT < t < T/2 21
4.5 Circuit analysis for time interval T/2 < t < T/2 + DT 23
4.6 Circuit analysis for time interval T/2 + DT< t < T 24
5 Summary 25
Chapter 3 The Proposed Circuit 27
1 Introduction 27
2 Operation principles 28
2.1 Assumptions 28
2.2 Mode 1: T0 < t < T1 31
2.3 Mode 2: T1 < t < T2 32
2.4 Mode 3: T2 < t < T3 33
2.5 Mode 4: T3 < t < T4 34
2.6 Mode 5: T4 < t < T5 35
2.7 Mode 6: T5 < t < T6 36
2.8 Mode 7: t > T6 37
3 Circuit analysis 38
3.1 Design of the module for CCM 38
3.2 Output voltage ripple reduction and component selection 39
4 Summary 41
Chapter 4 Experimental Results 42
1 Introduction 42
2 Circuit Design and Simulated Results 42
3 Experimental Result	47
4 Summary 61
Chapter 5 Conclusions and Future Researches 62
1 Conclusions	62
2 Future Researches 63
References 64
                                    

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校內：2012-12-02公開
校外：2012-12-02公開

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