近年來，伴隨資訊科技之蓬勃發展，各式電子產品及高速通訊電路中，皆須具備同時擁有高解析度及高轉換速度之類比-數位轉換器。因此本文即提出ㄧ輔以新式前置放大器，並具短暫穩定時間特色之二階式電容內插電路，以完成ㄧ顆具有10位元解析度，且每秒可處理超過兩億五千萬組資料之二階式類比-數位轉換器，同時並對功率消耗及抵消偏移電壓或雜訊干擾予以詳細之考量。而為驗證文中各電路設計之成果，本文使用電路模擬軟體HSPICE，並輔以 TSMC 0.18 1P6M CMOS製程來驗證架構中各電路之設計，而由模擬分析之結果，應有助於佐證本設計之可行性。

　　With the rapid development of information technology, an analog-to-digital converter is found critically needed in novel electronic products and high-speed communication circuits. Therefore, this paper has proposed a 10-bit two-step analog-to-digital converter embedded with the improved capacitor interpolation circuit as well as a novel amplifier, where the settling time is seen relatively short when compared to other methods. This completed converter can process 250 million samples per second. In the design, the low power consumption, voltage offset, and noise interference were all included into the considerations. To validate the effectiveness of this method, with the aid of TSMC 0.18 1P6M CMOS process, the circuit simulation software HSPIC was utilized, by which the simulation results obtained helped support the feasibility of the proposed design.

[1]　G. E. Moore,“Cramming More Components onto Integrated Circuits,”Electronics Magazine, Vol. 38, No. 8, April 1965.
[2]　T. Rengachari, V. Sharma, G. C. Temes, and U. Moon,“A 10-Bit Algorithmic A/D Converter for Cytosensor Application,” IEEE International Symposium on Circuits and Systems, Kobe, Japan, pp. 6186-6189, May 2005.
[3]　嚴祥銘，“1.8伏特十位元每秒135百萬次取樣速率二階式類比數位轉換器”，成功大學電機工程學系碩士論文， 2005年七月。
[4]　A. Wiesbauer et al., “A Fully Integrated Analog Front-End Macro for Cable Modem Applications in 0.18 CMOS,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 7, pp. 866-873, July 2002.
[5]　M. Clara, A. Wiesbauer, and F. Kuttner, “A 1.8V Fully Embedded 10 b 160MS/s Two-Step ADC in 0.18 COMS,” IEEE Custom Integrated Circuits Conference, Florida, U.S.A., pp. 437-440, May 2002.
[6]　R. Jacob Baker, CMOS Mixed-Signal Circuit Design, New York, John Wiley &Sons, 2002.
[7]　R. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd Edition, Kluwer Academic Publishers, 2003.
[8]　D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York, John Wiley &Sons, 1997.
[9]　B. Razavi, “Design of Sample-and-Hold Amplifiers for High-Speed Low-Voltage A/D Converters,” IEEE Custom Integrated Circuits Conference, Santa Clara, USA, pp. 59-66, May 1997.
[10]　K. Leelavattananon, C. Toumazou and J. B. Hughes, “Linearity Enhancement Techniques for MOSFET-ONLY SC Circuit,” IEEE International Symposium on Circuits and Systems, Switzerland, pp. 453- 456, May 2000.
[11]　B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Company, Boston, USA, 2001.
[12]　P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, New York, John Wiley &Sons, 2001.
[13]　G. M. Yin, F. O. Eynde and W. Sansen,“A High-Speed CMOS Comparator with 8-b Resolution,”IEEE Journal of Solid-State Circuits, Vol.27, No.2, pp. 208-211, February 1992.
[14]　R. Jacob Baker, H. W. Li and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation, New York, John Wiley &Sons, 1997.
[15]　S. Varma, K. Suyama and V. Gopinathan, “Analysis of Non-Idealities in Folding and Interpolating ADCs Using a Behavioral Model Approach,”IEEE International Symposium on Circuits and Systems, Atlanta, USA, pp. 508-511, May 1996.
[16]　L. Singer, S. Ho, M. Timko and D. Kelly, “A 12b 65MSample/s CMOS ADC with 82dB SFDR,” IEEE International Solid-State Circuits Conference, San Francisco, U.S.A, pp. 38- 39, February 2000.
[17]　P. M. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishi, K. Tanabe, and J. Vital, “A 90nm CMOS 1.2V 6b 1GG/s Two-Step Subranging ADC,” IEEE International Solid-State Circuits Conference, California, U.S.A., pp. 568- 569, February 2006.
[18]　K. Y. Kim, N. Kusayanagi, and A. A. Abidi,“A 10-bit,100 MS/s CMOS A/D Converter,”IEEE Custom Integrated Circuits Conference, San Diego, U.S.A, pp. 419-422, May 1996.
[19]　H. S. Chen, B. S. Song, and K. Bacrania,“A 14-b 20 Msamples/s CMOS pipelined ADC,”IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, pp. 997-1001, June 2001.
[20]　K. L. Lin, A. Kemna, and B. J. Hosticka, Modular Low-power, High-speed CMOS Analog-to-digital Converter For Embedded Systems, Boston, Kluwer Academic Publishers, 2003
[21]　J. Goes, J. Vital, and J. Franca, Systematic Design for Optimization of Pipelined ADCs, Boston, Kluwer Academic Publishers, 2001
[22]　G. Geelen,“A 6-b 1.1 GSample/s CMOS A/D Concerter,”IEEE International Solid-State Circuits Conderence, San Francisco, U.S.A., pp. 128-129, February 2001.
[23]　R. C. Taft and M. R. Tursi, “A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8 V down to 2.2V,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 3, pp. 331-338, March 2001.
[24]　I. Mehr and L. Singer,“A 55-mW, 10-bit, 40-MSample/s Nyquist-rate CMOS ADC,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 318-325, March 2000.
[25]　E. A. Vittoz and O. Neyround,“A Low-Voltage CMOS Bandgap Reference, ” IEEE Journal of Solid-State Circuits, Vol. SC-14, pp. 655-657, June 1979.
[26]　Y. Li, S. Yufeng, L. Lian, and Z. Zengyu,“CMOS bandgap voltage reference with 1.8-V power supply,”IEEE ASIC, 2003. Proceedings. 5th International Conference, Beijing, China, Vol. 1, pp. 611-614, October 2003.
[27]　A. R. Bugeja and B. S. Sing,“A Self-Trimming 14-b 100 MS/s CMOS DAC,” IEEE Journal of Solid-State Circuits, Vol. 24, pp. 1517-1522, December 1989.
[28]　C. L. Portmann and T. H. Y. Meng,“Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” IEEE Journal of Solid-State Circuits , Vol. 31, No. 8, pp. 1132-1140, August 1996.
[29]　A. G. W. Venes and R. J. van de Plassche,“An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, pp. 1846-1853, December 1989.
[30]　M Ferro, F. Salerno, and R. Castello,“A Floating CMOS Voltage Reference for Differential Applications,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, pp. 690-697, June 1989.
[31]　A. M. Abo and P. R. Gray,“A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 599-606, May 1999.