隨著積體電路製程的進步，以核心電路為基礎的單晶片系統設計方式逐漸成為IC設計產業中一個引人注目的趨勢。該設計方法具有提高晶片效能、縮短設計時程及降低製造成本等多項優點。然而，這樣的方式也帶來了許多新的挑戰，最嚴重的問題之一就是該如何測試此種單晶片系統。因此本論文提出一個利用嵌入式處理器控制的單晶片系統測試平臺來解決此種晶片的測試問題。
在所提出的測試平臺中，我們利用在單晶片系統中原本就存在的嵌入式處理器來執行一個測試程式藉以控制整個測試流程。這個測試程式藉由一些輔助電路的幫助，會對晶片中的核心電路進行結構性測試(structural testing)。本測試平臺可以測試那些加入如Boundary Scan或IEEE P1500之易測性設計的各種核心電路。此外，由於本測試平臺的內部元件採用了標準化的介面，所以可以應用在各類型的單晶片系統上。與近來所提出的各種單晶片系統測試架構比較，我們所提出的測試平臺減輕了對昂貴測試機台的需求，也因此大幅減少了測試成本。
為了驗証該測試平臺的實用性，我們設計了一個以ARM7處理器作為內嵌式處理器的單晶片系統電路，而其系統匯流排採用了AMBA AHB。實驗結果顯示出該單晶片系統測試平臺提供了一個可行的方法可用以解決單晶片系統的測試問題。

With the progress in VLSI technology, the core-based system-on-chip (SOC) design methodology is becoming an attractive solution in the IC design industry for its higher performance, shorter design time, and lower manufacturing cost. However, the SOC design also introduces many new challenges. One of the most critical problems is the testing of an SOC. In this thesis, an embedded-processor-driven platform for SOC testing is developed.
In this platform, an embedded processor in the SOC under test is employed as the control kernel to execute a test program. This program handles the structural testing of the IP cores in the SOC with the assistance of some extra circuitry. The platform supports the testing of cores that are wrapped by the standardized boundary scan wrappers or the IEEE P1500 wrappers. With a standardized interface, the proposed platform can be applied to different kinds of SOC designs of diverse functions. Compared with the test access mechanisms proposed recently, our methodology alleviates the need of expensive automatic test equipment, and hence can greatly reduce the total test cost.
To verify the practicability of the platform, an ARM-based SOC chip is developed with an ARM7 core as the embedded processor and an AMBA AHB bus as the backbone bus. Experimental results show the proposed platform is a feasible solution to the SOC test problem.

[1] IEEE P1500 Standard for Embedded Core Test (SECT) Web Site, http://grouper.ieee.org/groups/1500/.
[2] Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” in Proc. International Test Conference, pages 130 – 143, 1998.
[3] E.J. Marinissen et al., “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” in Proc. International Test Conference, pages 284-293, 1998.
[4] Lee Whetsel, “Addressable Test Ports An Approach to Testing Embedded Cores,” in Proc. International Test Conference, pages 1055-1065, 1999.
[5] M. Benabdenbi,W. Maroufi, and M. Marzouki, “CAS-BUS: a scalable and reconfigurable test access mechanism for systems on a chip,” in Proc. Design, Automation and Test in Europe (DATE), pages 141–145, 2000.
[6] K.-J Lee and C.-I. Huang, “A Hierarchical Test Control Architecture for Core Based Design,” in Proc. Asian Test Symposium, pages 248 -253, 2000.
[7] VSI Alliance Manufacturing-Related Test Development Working Group. “Test Access Architecture Standard (TST 2 1.0),” September 2001.
[8] R. Kapur, B. Keller, B. Koenemann, M. Lousberg, P. Reuter, T. Taylor, and P. Varma, “P1500-CTL: Towards a Standard Core Test Language,” in Proc. VLSI Test Symposium, pages 489-490, 1999.
[9] IEEE Computer Society, “IEEE Std. 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture,” 1990.
[10] Li Chen, S. Dey, P. Sanchez, K. Sekar, and Ying Chen, “Embedded Hardware and Software Self-Testing Methodologies for Processor Cores,” in Proc. Design Automation Conference, pages 625-630, 2000.
[11] G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, “Logic BIST for large industrial designs: real issues and case studies,” in Proc. International Test Conference, pages 358-367, 1999.
[12] D. Brahme and J.A. Abraham, “Test Generation for Microprocessors,” IEEE Transactions on Computers, Vol. C-33, pages 475-485, June 1984.
[13] A.J. van de Goor, T.J.W. Verhallen, “Functional Testing of Current Microprocessors (applied to the Intel i860),” in Proc. International Test Conference, page 684, 1992.
[14] J. Lee, J.H. Patel, “An Instruction Sequence Assembling Methodology for Testing Microprocessors,” in Proc. International Test Conference, page 49, 1992.
[15] L. Chen and S. Dey, “DEFUSE: A Deterministic Functional Self-Test Methodology for Processors,” in Proc. VLSI Test Symposium, pages 255-262, 2000.
[16] K. Batcher and C.A. Papachristou, “Instruction Randomization Self Test for Processor Cores,” in Proc. VLSI Test Symposium, pages 34-40, 1999.
[17] W.-C. Lai, A. Krstic, and K.-T. Cheng, “Test Program Synthesis for Path Delay Faults in Microprocessor,” in Proc. International Test Conference, pages 1080-1089, 2000.
[18] J. Shen and J.A. Abraham, “Native mode functional test generation for processors with applications to self test and design validation,” in Proc. International Test Conference, pages 990-999, 1998.
[19] W.-C. Lai and K.-T. Cheng, “Instruction-level DfT for testing processor and IP cores in system-on-a-chip,” in Proc. Design Automation Conference, pages 59-64, 2001.
[20] C.-H. Tsai and C.-W. Wu, “Processor-programmable memory BIST for bus-connected embedded memories,” in Proc. Design Automation Conference, pages 325-330, 2001.
[21] J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Processor-based built-in self-test for embedded DRAM,” IEEE Journal of Solid-State Circuits, pages 1731-1740, Nov. 1998
[22] R. Rajsuman, “Testing a System-On-a-Chip with Embedded Microprocessor,” in Proc. International Test Conference, pages 499-508, 1999.
[23] J.-R. Huang, M.K. Iyer, and K.-T. Cheng, “A self-test methodology for IP cores in bus-based programmable SoCs,” in Proc. VLSI Test Symposium, pages 198-203, 2001.
[24] C.A. Papachristou, F. Martin, and M. Nourani, “Microprocessor based testing for core-based system on chip,” in Proc. Design Automation Conference, pages 586-591, 1999.
[25] M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing,” Kluwer Academic Publishers, 2000.
[26] SynTest Technology, Inc., TurboScan User Guide, http://www.syntest.com/.
[27] SynTest Technology, Inc., TurboBIST-Memory User Guide, http://www.syntest.com/.
[28] “The Source For Perl,” http://www.perl.com.
[29] VSI Alliance On-Chip Bus Development Working Group. “Virtual Component Interface Standard (OCB 2 2.0),” April 2001.
[30] Muehldorf, “Designing LSI Logic for Testability,” in Proc. International Test Conference, 1976.
[31] PCI Special Interest Group, Hillsboro, Oregon, USA. PCI Local Bus Specification, Revision 2.0, April 1994.
[32] ARM7 Data Sheet, http://www.arm.com.
[33] AMBA Specification, http://www.arm.com.