近年來由於超大型積體電路運作時脈的頻率快速地增加，使得電路效能大為提升。然而在電路較複雜且運作時脈較快的情況下，電路運作的正確性有待考驗。在超大型積體電路中，時脈信號的正確性關係著系統能否正常運作，針對時脈相位的校正電路，類如鎖相迴路PLL (Phase-locked loop)或延遲鎖定迴路DLL (Delay-locked loop)，目前已有相當不錯的研究成果。
訊號在經過多個邏輯閘或是緩衝器(Buffer)後，由於電晶體的不匹配，訊號上升與下降時間難以完全一致，致使信號的脈寬增大或變小。信號脈寬失真的結果往往造成電路的錯誤動作，所以對於脈寬的調整上，開始有不少相關的研究呈現。本論文採用全數位的方式來設計脈寬鎖定迴路，所完成的電路除了具有不限單一輸入時脈信號頻率、不限50%的脈波寬度的特性之外，相較於傳統之脈寬鎖定迴路，在鎖定時間上亦有大幅度的改善。
本論文提出的電路主要使用TSMC 0.18 μm 1P6M的製程來進行設計與模擬驗證。模擬結果顯示其操作頻率範圍為330 MHz~500 MHz之間。電路耗費的功率為13 mW，可在50 ns以內完成趨近的脈寬輸出穩定值，核心佈局耗費面積為250 μm × 310 μm。

In recent years, semiconductor integrated circuits exhibit significant performance improvements as the operating frequency increases. However, it is not easy to ensure the signal integrity, especially when the circuit is complicated and operated in high clock frequency. The clock signal is important because the quality of clock signal usually decides whether the system works correctly or not. Phase-locked loop (PLL) and delay-locked loop (DLL) integrated circuits are frequently used to generate highly accurate phases of internal clock signals. There are lots of investigations and excellent achievements on these two circuits in recent years.
When a clock signal passed through many stages of logic gate and/or buffer, owing to the mismatch of MOS transistors, the rising and falling times of the clock are usually different. Consequently, the clock duty cycle might be enlarged or shrunk, which would cause afflictive signal integrity problems. Therefore, plenty of researches on adjusting the pulsewidth of the clock have been presented. This thesis presents an all-digital pulsewidth locked loop design which can be operated in various clock frequencies and duty cycles. In addition, comparing with conventional pulsewidth locked loop, the presented design has shorter lock-in time.
All major function blocks presented in this thesis are all verified and simulated with TSMC 0.18 um 1P6M CMOS process. The range of operating frequency in this design is from 330 MHz to 500 MHz. Total power consumption of the proposed pulsewidth locked loop is about 13 mW and the output pulsewidth can be nearly approached the ideal value steadily within 50 ns. The core area of this design is about 250 um*310 um.

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