簡易檢索 / 詳目顯示

回結果列表
研究生： 林宗賢
Lin, Tsung-Hsien
論文名稱： 具數位背景校正技術之十二位元每秒三十億次四倍分時導管式類比數位轉換器
A 12-bit 3GS/s 4xTI Pipelined ADC with Digital Background Calibration
指導教授： 郭泰豪
Kuo, Tai-Haur
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 80
中文關鍵詞： 直接射頻取樣, 分時多工, 背景式誤差校正, 導管式類比數位轉換器
外文關鍵詞： direct-sampling, time-interleaved, background calibration, pipelined ADC
相關次數： 點閱：117  下載：22 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本篇論文實現一個適用於直接射頻取樣接受器的十二位元每秒三十億次四倍分時導管式類比數位轉換器，於本文中提出了多級校正的方式來達到低功耗實現，此外還採用一個針對比較器偏移誤差的校正技術進行輔助，可以提高單級解析度並同時降低整體功耗與潛時。最後使用了三級的架構實現在台積電40奈米1P9M互補型金氧半導體製程，在1.33GHz的輸入頻率下，SNDR達到58.79dB，Schreier FoM與Walden FoM分別為157dB與102fJ/convertion-step，在1V的操作電壓下，整體功耗為218mW。

    This thesis presents a 12-bit 3GS/s 4x time-interleaved (TI) pipelined analog-to-digital converter (ADC) for direct-sampling receiver system. Calibration for multi-stage is proposed for achieving low power. Moreover, a comparator offset calibration technique is assisted to achieve a higher resolution of single stage and reduce the total power consumption and the latency in the same time. A three-stage structure is implemented in TSMC 40nm 1P9M CMOS process. The ADC achieves an SNDR of 58.79 dB, a Schreier FoM of 157 dB, and a Walden FoM of 102 fJ/conversion-step for a 1.33 GHz input. The ADC consumes 218mW from a 1V supply.

    Chapter1 Introduction 1 1.1 Motivation 1 1.2 Organization 3 Chapter2 Error Analyses of Time-interleaved (TI) Pipelined ADC 4 2.1 Quantization error 4 2.2 Noise 5 2.3 Clock jitter 10 2.4 Comparator offset in sub-ADC 12 2.4.1 Effect of comparator offset 12 2.4.2 Digital error correction (DEC) 16 2.5 Sampling mismatch between sub-ADC and MDAC 17 2.6 Error in MDAC 18 2.7 Channel mismath of TI-ADC 19 2.7.1 Offset error mismatch 20 2.7.2 Gain error mismatch 20 2.7.3 Timing mismatch 21 Chapter3 Calibration Techniques 23 3.1 Introduction of the prior art 23 3.2 Step-shifted background calibration (SSBC) 28 3.2.1 Introduction 28 3.2.2 Architectures 29 3.2.3 Error detection and correction 33 3.3 Split-ADC background calibration 34 3.3.1 Introduction 34 3.3.2 Architecture 35 3.3.3 Error detection and correction 35 Chapter4 Proposed Pipelined ADC with Calibration Techniques 40 4.1 Multi-bit per stage vs. conventional 1.5-bit per stage 40 4.2 Multi-bit stage with SSBC and split-ADC background calibration 41 4.3 Decision of bit number of each stage 44 4.3.1 Limitatons of bit number number per stage 44 4.3.2 Scaling between stages 46 4.3.3 Architecture of proposed ADC 51 Chapter5 Circuit Implementation 53 5.1 Time-interleaved sample-and-hold circuit 53 5.1.1 Global sampling technique 54 5.1.2 Input-feedtrough prevention 55 5.2 Sub-ADC with SSBC technique 56 5.2.1 Adjustable dynamic comparator 56 5.2.2 Calibation circuit 56 5.3 1st MDAC 60 5.3.1 Sub-DAC with chopping and SSBC decode logic 60 5.3.2 Two stage charge steering amplifier 62 5.4 Backend stages 66 5.4.1 2nd stage 66 5.4.2 3rd stage 67 5.5 Phase generator 68 5.5.1 Clock receiver 68 5.5.2 Multi-phase clock generator 68 5.5.3 Phase allocation circuit 69 5.6 Digital backend 70 5.6.1 Decoder of flash ADC 70 5.6.2 Timing aligning circuit 72 Chapter6 Simulation Results and Comparison Table 73 6.1 Simulation results 73 6.2 Comparison table 75 Chapter7 Conclusion and Future Work 76 Reference 77

    [1] Hegong Wei, Peng Zhang, Bibhu Datta Sahoo, and Behzad Razavi, " An 8 Bit 4 GS/s 120 mWCMOS ADC," IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1751-1761, Aug. 2014.
    [2] Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High-Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.
    [3] Kattmann, K. and Barrow, J., "A Technique For Reducing Differential Non-linearity Errors In Flash A/D Converters," in 1991 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 1991.
    [4] William C. Black, JR., and David A. Hodges, "Time Interleaved Converter Arrays," IEEE J. Solid-State Circuits, vol. 15, no. 6, pp. 1022-1029, Dec. 1980.
    [5] Renuka P. Jindal, "Compact Noise Models for MOSFETs," IEEE trans. Electron Devices, vol. 53, no. 9, pp. 2051-2061, Sep. 2006.
    [6] Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, and Geert Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441-1454, Jul. 2008.
    [7] Shiuh-Hua Wood Chiang, Hyuk Sun, and Behzad Razavi, "A 10-Bit 800-MHz 19-mW CMOS ADC," IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 935-949, Apr. 2014.
    [8] Marcel J. M. Pelgrom, Aad C. J. Duinmaijer, and Anton P. G. Welbers, "Matching Properties of MOS Transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
    [9] Patrick G. Drennan and Colin C. McAndrew, "Matching Properties of MOS Transistors," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450-456, Mar. 2003.
    [10] Stephen H. Lewis, H. Scott Fetterman, George F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample / s Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992.
    [11] Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan et al., "SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration," IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1893-1903, Aug. 2011.
    [12] Naoki Kurosawa, Haruo Kobayashi, Kaoru Maruyama, Hidetake Sugawara, and Kensuke Kobayashi, "Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems, " IEEE Trans. Circuits Syst. I, vol. 48, no. 3, pp. 261-271, Mar. 2001.
    [13] Benjamin Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, and Un-Ku Moon, "Ring Amplifiers for Switched Capacitor Circuits," IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2928-2942, Dec. 2012.
    [14] B. Robert Gregoire and Un-Ku Moon, "An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain" IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2620-2630, Dec. 2008.
    [15] Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto, "A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration," in 2010 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2010.
    [16] Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, and Klaas Bult, "An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2834-2844, Dec. 2011.
    [17] Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu, "A 21fJ/conv-step 9 ENOB 1.6GS/s 2× Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS," in 2015 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2015.
    [18] Vanessa Hung-Chu Chen, Lawrence Pileggi, "A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI," in 2014 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2014.
    [19] Chun-Cheng Huang and Jieh-Tsorng Wu, "A Background Comparator Calibration Technique for Flash Analog-to-Digital Converters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 1732-1740, Sep. 2005.
    [20] Chun-Ying Chen, Jiangfeng Wu, Juo-Jung Hung, Tianwei Li, Wenbo Liu, and Wei-Ta Shih, "A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm and 500 mW in 40 nm Digital CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1013-1021, Apr. 2012.
    [21] Jiangfeng Wu, Chun-Ying Chen, Tianwei Li, Lin He, and et al., "A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization," IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1818-1828, Aug. 2013.
    [22] Ahmed M. A. Ali, Huseyin Dinc, Paritosh Bhoraskar, Chris Dillon, and et al., "A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration," IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2857-2867, Dec. 2014.
    [23] Bibhu Datta Sahoo and Behzad Razavi, " A 10-b 1-GHz 33-mW CMOS ADC" IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1442-1452, Jun. 2013.
    [24] Brian Setterberg, Ken Poulton, Sourja Ray, Dan J. Huber, and et al., " A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction," in 2013 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2013.
    [25] 張君豪（民103）。具步階位移背景誤差校正之8位元2GS/s快閃類比數位轉換器（未出版之碩士論文）。國立成功大學，台南市。
    [26] John McNeill, Michael C. W. Coln, and Brian J. Larivee, "“Split ADC” Architecture for Deterministic Digital Background Calibration of a 16-bit 1-MS/s ADC," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437-2445, Dec. 2005.
    [27] 廖凡緯（民105）。具背景校正技術十四位元每秒八億次四倍分時導管式類比數位轉換器（未出版之碩士論文）。國立成功大學，台南市。
    [28] Boris Murmann, Bernhard E. Boser, "A 12b 75MS/s Pipelined ADC using Open-Loop Residue Amplification," in 2003 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2003.
    [29] Bibhu Datta Sahoo and Behzad Razavi, "A 10-b 1-GHz 33-mW CMOS ADC," IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1442-1452, Jun. 2013.
    [30] James Lin, Masaya Miyahara and Akira Matsuzawa, "A 15.5 dB, Wide Signal Swing, Dynamic Amplifier Using a Common-Mode Voltage Detection Technique," in 2011 IEEE Int. Symposium of Circuit and System (ISCAS), 2011.
    [31] Frank van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, and Klaas Bult, "A 1.5 mW 68 dB SNDR 80 Ms/s 2 Interleaved Pipelined SAR ADC in 28 nm CMOS," IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2835-2845, Dec. 2014.
    [32] David W. Cline and Paul R. Gray, "A Power Optimized 13-b 5 Msample/s Pipelined Analog-to-Digital Converter in 1.2 um CMOS ," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294-303, Mar. 1996.
    [33] Andrew M. Abo and Paul R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May. 1999.
    [34] Mikael Gustavsson and Nianxiong Nick Tan, "A Global Passive Sampling Technique for High-Speed Switched-Capacitor Time-Interleaved ADCs," IEEE Trans. Circuits Syst. II, vol. 47, no. 9, pp. 821-831, Sep. 2000.
    [35] Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, and Gerard van der Weide, "A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2821-2833, Dec. 2011.
    [36] Xiang Gao, Student Eric A. M. Klumperink, and Bram Nauta, "Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation," IEEE Trans. Circuits Syst. II, vol. 55, no. 3, pp. 244-248, Mar. 2008.
    [37] Ahmed M.A. Ali, Huseyin Dinc, Paritosh Bhoraskar, Scott Puckett, and et al., "A 14-bit 2.5GS/s and 5GS/s RF Sampling ADC with Background Calibration and Dither," in 2016 IEEE Symposuim on VLSI Circuits (VLSI-Circuits), 2016.
    [38] Matt Straayer, Jim Bales, Dwight Birdsall, Denis Daly, Phillip Elliott, Bill Foley, Roy Mason, Vikas Singh, and Xuejin Wang, "A 4GS/s Time-Interleaved RF ADC in 65nm CMOS with 4GHz Input Bandwidth," in 2016 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2016.
    [39] Jiangfeng Wu, Acer Chou, Tianwei Li, Rong Wu, and et al., "A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS," in 2016 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2016.
    [40] Jiangfeng Wu, Acer (Wei-Te) Chou, Cheng-Hsun Yang, Yen Ding, and et al., "A 5.4GS/s 12b 500mW Pipeline ADC in 28nm CMOS Jiangfeng," in 2016 IEEE Symposuim on VLSI Circuits (VLSI-Circuits), 2016.
    [41] Brian Setterberg, Ken Poulton, Sourja Ray, Dan J. Huber, and et al., "A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction," in 2013 IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers (ISSCC), 2013.

    下載圖示 校內：2020-02-03公開
    校外：2020-02-03公開
    QR CODE