近年來隨著CMOS製程往7nm以下微縮，鰭式場效電晶體(FinFET)對通道的控制力逐漸不足，環繞式閘極(GAA)結構因此被提出來，用以解決原結構在工藝微縮過程中對通道控制力式微的問題。其中，具有環繞式閘極結構的互補式場效電晶體(CFET)將N型電晶體與P型電晶體垂直堆疊起來，提升了晶片微縮的可能性，因而成為了下一世代CMOS工藝技術發展的的候選者。而對於CFET工藝，台灣半導體研究中心(TSRI)提出具有多晶矽通道的無接面式CFET，其製程具有低溫且易三維堆疊的特性，因而適用於積層型三維製程整合(monolithic 3D integration)。
在此論文中，我們針對TSRI研製之CFET工藝，利用其潛力將它以積層型三維製程整合的方式與傳統CMOS結合，應用在以靜態隨機存取記憶體(SRAM)為基礎之記憶體內運算(CIM)電路設計上，藉以顯著地減少晶片面積。我們以7nm工藝節點為假設基礎，經由一系列的模擬及對三維堆疊的電路架構提出操作概念，評估出據此製程概念及架構所製作出的CIM電路應用在以在神經型態運算執行影像辨識的效能，並與傳統CMOS工藝的表現做比較。
在具體模擬的執行上：我們以CFET元件電流-電壓特性的實驗數據萃取出SPICE模型及元件變異性，並針對製程及元件本身尚不理想的問題，做了些許假設，將SPICE模型做了調整，使特性趨於理想，並以此些模型為基礎，執行對單顆6T-SRAM cell基本特性的調查，再執行以8T-SRAM陣列為基礎的CIM電路的模擬（模擬中有加入以7nm工藝估計出的RC參數使模擬更加完善）。根據SPICE的模擬結果，萃取適當的特徵輸入由我們實驗室開發的CIM&AI模擬平台當中，評估其在CIM&AI應用上的表現，包含準確率、延遲、功耗、佔據面積及單位功耗下單位時間內所執行的運算次數。

In recent years, FinFET's electrostatic control over the channel gradually degrades as CMOS technology scales towards the sub-7nm regime. Thus, gate-all-around (GAA) structure is proposed in order to solve the degraded electrostatic control over the channel. Particularly, complementary-FET (CFET), which has vertically stacked NFET and PFET with a GAA common gate, is a promising candidate for next-generation CMOS technology due to its potential for scaling down. For CFET development, TSRI proposes a polysilicon-channel junctionless CFET structure, which is fabricated at low temperature and easy to stack in 3D, is suitable for monolithic 3D integration.
In this thesis, we aim to leverage the potential of TSRI's CFET technology and apply this technology towards SRAM-based Compute-in-Memory (CIM) circuits by monolithically integrating this technology with the conventional CMOS in 3D to design CIM circuits with significantly reduced chip area consumption. We assume that the CIM circuits are fabricated at the 7nm technology node and performed a series of simulations with a particular operational scheme of the 3D-stacked circuits. Finally, the performance of the CIM-based neuromorphic computing applied on image recognition is evaluated. The performance of the conventional CMOS technology is evaluated to make a comparison.
In the practical simulations, the SPICE models and the device variations are extracted based on the experimental I-V data, and some of the model parameters are tuned based on some assumptions to improve the device performance. With the SPICE models, the basic properties of 6T-SRAM cell are investigated, and then the simulations for the CIM circuits based on the 8T-SRAM array are performed. (RC-related parameters of the 7nm technology node are estimated and included in the simulations to make the simulations more precise.) Based on the results of SPICE simulations, behavioral features are extracted and included in the CIM&AI simulation platform developed by our lab to evaluate the performance of CIM&AI applications, including accuracy, latency, power, consumed area, and TOPS/W.

[1] J. Ryckaert et al., "The Complementary FET (CFET) for CMOS scaling beyond N3," in 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2018.
[2] S. -W. Chang et al., "First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications," in 2019 IEEE International Electron Devices Meeting (IEDM), Francisco, CA, USA, 2019.
[3] S. Jones, "VLSI Symposium 2020 – Imec Monolithic CFET," 13 Sep 2020. [Online]. Available: https://semiwiki.com/semiconductor-services/290804-vlsi-symposium-2020-imec-monolithic-cfet/.
[4] B. Vincent, "Introducing Nanosheets into Complementary-Field Effect Transistors (CFET)," 26 May 2020. [Online]. Available: https://www.coventor.com/blog/introducing-nanosheets-complementary-field-effect-transistors-c-fet/.
[5] Q. Dong et al., "A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications," in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020.
[6] J. Su et al., "A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips," in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020.
[7] J. P. Duarte et al., "BSIM-CMG: Standard FinFET compact model for advanced circuit design," in ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015.
[8] Y. S. Chauhan et al., FinFET Modeling for IC Simulation and Design:Using the BSIM-CMG Standard, San Francisco, CA, USA: Academic Press, 2015.
[9] R. Bao, M. A. Guillorn, T. Hook, R. R. Robison, R. Vega and T. Yamashita, "GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD VOLTAGES". US Patent 20200251568, 6 Aug 2020.
[10] Michele Amato et al., "Work function bowing in Si1−xGex heterostructures: Ab initio results," Journal of Applied Physics. 119(8), 25 Feb 2016.
[11] E. Grossar, M. Stucchi, K. Maex and W. Dehaene, "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies," IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov 2006.
[12] B. H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, Jul 2006.
[13] Hiroshi Makino et al., "Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration," Circuits and Systems, vol. 3 no. 3, pp. 242-251, Jan 2012.
[14] Md. Aftab Baig, Cheng-Jui Yeh et al., "3D Heterogeneous Integration of Complementary-FET with CMOS for Next Generation Compute-in-Memory," submitted to VLSI Symposium 2021.
[15] I. Ciofi et al., "Impact of Wire Geometry on Interconnect RC and Circuit Delay," IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2488-2496, Jun 2016.
[16] P. Singer, "Scaling the BEOL: A Toolbox Filled with New Processes, Boosters and Conductors," 8 Feb 2020. [Online]. Available: https://www.semiconductor-digest.com/2020/02/08/scaling-the-beol-a-toolbox-filled-with-new-processes-boosters-and-conductors/.
[17] Sung Hyun Jo et al., "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Letters, vol. 10, no.4, pp. 1297-1301, 2010.