在以相同的影像品質的前提下，H.264/AVC 相較於MPEG-2及MPEG-4可以節省了大約60%與40%的位元率。所以近年來他被廣泛的運用在多媒體通訊及消費性電子產品上如數位電視、高畫質DVD、視訊電話等等。
H.264使用了RDO(碼率-失真最佳化)來決定編碼的模式才可以達到如此高的編碼效能，而為了在幅內預測中取得最佳的模式，編碼器必須去計算所有可能模式的RDO，並且選擇最小值的模式當作我們要的最佳模式；由於在H.264 4×4的區塊大小中總共有九種模式，16×16的區塊大小則有四種模式，每編碼一個巨區塊就必需重複作RDO的運算已取得最佳的模式，如果需要兼顧良好的影像品質及有效率的編碼，那麼RDO的運算會是一個很大的負擔。
為了解決這個問題，我們提出了預先決定區塊大小、粗略的方向追蹤、提前終止等三個方法，並透過參考軟體JM驗證演算法，接著使用Verilog硬體描述語言來實現其RTL之電路架構，再使用TSMC® 0.18μm製程以Synopsys®的Design Compiler作合成，最終完成可以減少整體編碼75%運算量以及運算速度可達到250 MHz。

H.264/AVC can achieve about 60% bit rate saving compared to MPEG-2, and about 40% bit rate saving over MPEG-4 with the same video quality. In recent years, H.264/AVC is widely used for multimedia communications and consumer electronics such as Digital TV, High Definition DVD, Camera Phone, and others.
To achieve high coding efficiency, H.264/AVC uses Lagrangian rate distortion optimization (RDO) technique to decide the coding mode. In order to choose the best coding mode for intra prediction, the encoder has to calculate the RDO of every possible mode and choose the mode having the minimum value. This process is repeatedly carried out for every possible mode in a macroblock. For each macro block, there are nine prediction modes in 4×4 luma block , and four modes 16×16 luma block. If the encode obtains both good quality and high efficiency, it requires large amounts of RDO calculations.
To address this issue, we propose block size decision, direction tracing with coarse prediction, and early termination. We verify the proposed algorithm through the reference software Joint Model and implement the RTL code by Verilog hardware description language. We synthesize the digital circuit by using Design Compiler of Synopsys with the TSMC 0.18μm CMOS μm technology. Finally, the proposed intra prediction algorithm can reduce 75% computational time and the low complexity hardware can work up to 250MHz.

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