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研究生：	鍾錦翰 Chung, Chin-Hun
論文名稱：	低電容橫向式暫態電壓抑制器模擬與製成 Simulation and Fabrication of Low Capacitance Lateral Transient Voltage Suppressor
指導教授：	李文熙 Lee, Wen-Hsi
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2014
畢業學年度：	102
語文別：	英文
論文頁數：	46
中文關鍵詞：	靜電放電、靜電防護、暫態電壓抑制器、箝制電壓
外文關鍵詞：	ESD, Electrostatic Discharge, TVS, Clamping Voltage
相關次數：	點閱：188 下載：7
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隨著電子產品逐漸精密，尺寸不斷縮小，工作速度不斷增加，IC元件更容易受靜電放電(Electrostatic Discharge/ESD)的破壞，此時也產生更高效能的保護元件需求。暫態電壓抑制器(Transient Voltage Suppressor/TVS)為ESD靜電防護的主流。本論文研究主題是雙向陣列式的TVS元件，利用串接的設計來降低元件電容，以提高反應速度。本論文首先以Silvaco TCAD軟體模擬此元件的結構，並設定多組製程參數求得最佳化條件。接著使用Tanner L-Edit軟體做光罩設計並在晶圓廠投片試產，再到封裝廠完成封裝製程後對成品做電性量測，比較實際產品與軟體模擬的電性差異。箝制電壓測量值平均為7.4V，I/O間電容為0.52pF，I/O到地電容為1.073pF。箝制電壓的部分，實際產品與模擬軟體的結果差距甚小，但電容部分相差較大。推測應該是晶片電容值會因封裝而有所改變，且模擬所得的電容計算方式較為理想化精簡化。

Technology advances has shrunk the size of integrated circuits, making portable devices much more available and one of the major class of consumer electronics. However, these IC’s are more vulnerable to Electrostatic Discharge (ESD) hazard, since their reduced dimensions leads to problems such as a more penetrable oxide layer caused by reduced oxide thickness. Lower operating voltage also requires stricter protection devices. Besides, the operating speed of modern devices has increased dramatically. These all sum up to the need of a transient voltage suppressor, or TVS, which is designed to protect the IC’s from ESD and electrical surges with a respond speed that matches the electronics today.
In this thesis, the Silvaco TCAD software is used to simulate the fabrication and electric characteristics of a bi-directional lateral TVS. The parameters for the desired characteristics are found through simulation. Tannar L-Edit software is then used to design photo mask and tape-out wafers in FAB for engineer pilot run. Measurement data of the actual device fabricated is collected and compared with the simulation result. The clamping voltage measured is about 7.4V, which is close to the simulation result. The I/O to I/O capacitance is about 0.52pF, while the capacitance between I/O and ground is about 1.073pF. These measured values are different from the ones simulated. The cause to these differences may be the overly simplified calculation for the equivalent capacitance. The packaging material also contributes to the overall capacitance, making the actual value larger than the simulated one.

TABLE OF CONTENTS
摘要…………………………………………………………………………...………..I
ABSTRACT…………………………………………………………………………..II
致謝…………………………………………………………………………………..III
TABLE OF CONTENTS…………………………………………………….............VI
LIST OF TABLES………………………………………………………………......VII
LIST OF FIGURES………………………………………………………...……....VIII
CHPATER 1 INTRODUCTION………………………………………………………1
1.1 Preface……………………………………………………………………….1
1.2 Research Motivation and Goal……………………………………………….2
1.3 Chapters Preview……………………………………………………….…….2
CHAPTER 2 LITERATURE REVIEW……………………………………………….3
2.1 ESD………………………………………………………………………..…3
2.2 TVS Device and Characteristics……………………………………………...3
2.2.1 TVS Working Principle……………………………………………….3
2.2.2 Parameters Regarding TVS…………………………………………..5
2.2.3 Breakdown Mechanisms……………………………………………...7
2.2.4 Low Capacitance TVS……………………………………………….13
2.2.5 TVS Array………………………………………………………...…14
CHAPTER 3 EXPEREMENTAL SECTION……………………………………...…15
3.1 Experiment Procedure…………………………………………………....…15
3.2 Device Design………………………………………………………………16
3.3 Device Simulation…………………………………………………………..17
3.3.1 Zener Diode………………………………………………………….18
3.3.2 High-side Driving Diode…………………………………………….24
3.3.3 Low-side Driving Diode…………………………………………..…27
CHAPTER 4 RESULTS AND DISCUSSION……………………….………............31
4.1 Electric Characteristics Measurements……………………………………..31
4.1.1 Clamping Voltage………………..………………………………..…31
4.1.2 Device Capacitance……………………………………………….…32
4.1.3 Breakdown Voltage………………………………………………..…32
4.2 SEM Analysis…………………………………………………….…………33
4.2.1 Device Top View…………………………………………………….33
4.2.2 Zener Diode……………………………………………………...…..34
4.2.3 High-side Driving Diode…………………………………………….36
4.2.4 Low-side Driving Diode………………………………………..……37
4.3 Comparison with Simulation Data……………………………………….…38
4.3.1 Breakdown Voltage………………………………………………..…38
4.3.2 Capacitance…………………………………………………………..38
CHAPTER 5 CONCLUSION………………………………………………………..44
REFERENCES……………………………………………………………………….45

LIST OF TABLES
Table 3.1 Process Flow of Simulation………………………………………………..17
Table 3.2 Simulated breakdown voltage of zener split conditions…………………...19
Table 3.3 Simulated capacitance of zener split conditions………………...…………24
Table 3.4 Simulated capacitance of high-side diode split conditions………………...25
Table 3.5 Simulated capacitance of low-side diode split conditions………………....29
Table 4.1 Measurement of Device Clamping Voltage………………………………..33
Table 4.2 Measurement of Device Capacitance…………………………………...…34
Table 4.3 Comparison between simulation and measurement data………………….45

LIST OF FIGURES
Figure 2.1 TVS working principle………………………………………………….…5
Figure 2.2 I-V characteristic of a uni-directional TVS………………………………..7
Figure 2.3 Zener diode………………………………………………………………...8
Figure 2.4 Schematic diagram of a p-n junction………………………………………9
Figure 2.5 Charge density across the junction………………………………………...9
Figure 2.6 The carrier density across a one-sided abrupt junction……………….…..11
Figure 2.7 General structure of a vertical TVS………………………………………12
Figure 2.8 General structure of a lateral TVS……………………………………..…12
Figure 2.9 Diode string……………………………………………………………….13
Figure 2.10 Capacitance connected in series…………………………………………13
Figure 2.11 Circuit configuration of a TVS array with four I/Os…………………….14
Figure 2.12 SOT-363 Packaging………………………..……………………………14
Figure 3.1 Experiment procedure………………………………………………….…15
Figure 3.2 Cross-sectional view of the proposed device……………………………..16
Figure 3.3 Circuit connections of device terminals…………………………………..16
Figure 3.4 Simulated I-V curves of zener split conditions…………………………...19
Figure 3.5 Simulated I-V curves of zener split conditions………………………...…20

Figure 3.6 Acceptor distribution of the zener with p-body implant of 1e13 (dose/cm2)
	…………………………………………………………………………………..20
Figure 3.7 Acceptor distribution of the zener with p-body implant of 2e13 (dose/cm2)
	…………………………………………………………………………………..20
Figure 3.8 Acceptor distribution of the zener with p-body implant of 4e13 (dose/cm2)
	…………………………………………………………………………………..21
Figure 3.9 Electric field vectors of zener with p-body implant of 1e13 (dose/cm2)
	…………………………………………………………………………………..21
Figure 3.10 Electric field vectors of zener with p-body implant of 2e13 (dose/cm2)
	………………………………………………………………………………..…21
Figure 3.11 Electric field vectors of zener with p-body implant of 4e13 (dose/cm2)
	…………………………………………………………………………………..22
Figure 3.12 Net doping concentration (left) and electric field in relation to the device
depth of zener with the 1e13 p-body implant…………………………………...23
Figure 3.13 Net doping concentration (left) and electric field in relation to the device
depth of zener with the 2e13 p-body implant…………………………………...23
Figure 3.14 Net doping concentration (left) and electric field in relation to the device
 	depth of zener with the 4e13 p-body implant…………………………………...24

Figure 3.15 Net doping concentration of high-side diode with P/2e13/100KeV implant
	…………………………………………………………………………………..26
Figure 3.16 Net doping concentration of high-side diode with P/2e13/140KeV implant
	………………………………………………………………………………..…26
Figure 3.17 Net doping concentration of high-side diode with P/2e13/180KeV implant
	…………………………………………………………………………………..26
Figure 3.18 Net doping concentration (left) and electric field (right) in relation to the
device depth of high-side diode with the P/2e13/100KeV n-well implant……..26
Figure 3.29 Net doping concentration (left) and electric field (right) in relation to the
device depth of high-side diode with the P/2e13/140KeV n-well implant……..27
Figure 3.20 Net doping concentration (left) and electric field (right) in relation to the
device depth of high-side diode with the P/2e13/180KeV n-well implant……..27
Figure 3.21 Net doping concentration of low-side diode with P/2e13/100KeV implant
	………………………………………………………………………………..…28
Figure 3.22 Net doping concentration of low-side diode with P/2e13/140KeV implant
	…………………………………………………………………………………..29
Figure 3.23 Net doping concentration of low-side diode with P/2e13/180KeV implant
	…………………………………………………………………………………..29

Figure 3.24 Net doping concentration (left) and electric field (right) in relation to the
device depth of low-side diode with the P/2e13/100KeV n-well implant……...29
Figure 3.25 Net doping concentration (left) and electric field (right) in relation to the
device depth of low-side diode with the P/2e13/140KeV n-well implant……...30
Figure 3.26 Net doping concentration (left) and electric field (right) in relation to the 	device depth of low-side diode with the P/2e13/180KeV n-well implant……...30
Figure 4.1 Top view of the proposed TVS device…………………………………....33
Figure 4.2 Cross-sectional view of the zener section………………………………...34
Figure 4.3 Cross-sectional view of the zener section………………………………...35
Figure 4.4 Cross-sectional view of the zener section………………………………...35
Figure 4.5 Cross-sectional overview of the high-side array………………………….36
Figure 4.6 Close-up cross-sectional view of the high-side diode………………….…36
Figure 4.7 Cross-sectional overview of the low-side array………………………..…37
Figure 4.8 Close-up cross-sectional view of the low-side diode…………………….37
Figure 4.9 Equivalent circuit of pin to ground capacitance………………………….39
Figure 4.10 Equivalent circuit of pin to ground capacitance………………………...39
Figure 4.11 Equivalent circuit of pin to pin capacitance……………………………..40
Figure 4.12 Equivalent circuit of pin to pin capacitance……………………………..40
Figure 4.13 Equivalent circuit of pin to pin capacitance…………………………..…41

                                    

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