本文提出一低輸出電流漣波高降壓比轉換器。基於伺服器電源的架構改變，傳統的12 V輸入電壓被提升至48 V，而微處理器之工作電壓為1 V左右，此時傳統的降壓電路將無法提供足夠之降壓比，故提出此架構來達到高降壓之功能。相較於其他現有架構，此架構能夠透過適當之開關導通率來達到相同之轉換比。此架構也結合了交錯式結構，能夠分散輸出電流，降低電路之導通損。除此之外，此交錯式結構能夠有效的降低輸出電流漣波，進而縮小輸出濾波元件的體積。此電路具有五顆開關元件，其中四顆於切換時會與漏感諧振，達到零電壓切換，得以減少開關的切換損。本文其後將會針對電路之動作原理、穩態分析以及電路元件的參數的設計進行詳細的說明。
最後，根據本文所提出之設計流程，研製一具輸入電壓為48 V、輸出電壓為1 V以及輸出功率為30 W 之雛形電路，對本文所提出之電路進行實現與驗證。

In this thesis, an “Ultra-High Step-Down Ratio Converter with Extended Duty Cycle and Low Output Current Ripple” is proposed. Due to the change of the server and distribution infrastructure, eliminating 12 V intermediate conversion stage, a high step-down voltage converter is required to convert 48 V bus voltage to the operating voltage of microprocessor as low as 1 V. Proposed converter can achieve the required conversion ratio with an adequate duty cycle compared to the other topologies. Furthermore, this converter has an inherent interleaved structure, which can share the currents, reduce the conduction loss. Besides, interleaved structure can reduce the output current ripple and thus shrink the size of output filter. On the other hand, four out of five switches will resonate with leakage inductor and therefore can be turned on with ZVS, thus enhancing the conversion efficiency. In this thesis, operating principles, steady-state analysis, and component parameter designs are presented. Finally, a hardware prototype with 48 V input voltage, 1 V output voltage, and 30 W output power is implemented to verify the feasibility of the proposed converter.

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