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研究生： 吳健福
Wu, Jian-Fu
論文名稱： 一個六位元每秒十億次取樣頻率的類比/數位轉換器
A 6-bit 1-Gsample/sec Analog-to-Digital Converter
指導教授： 林克旯
Lin, Keh-la
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 中文
論文頁數： 62
中文關鍵詞： 快閃式類比數位轉換器 、讀取通道 、類比數位轉換器
外文關鍵詞： flash adc, read channel, A/D converter
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    • 　　本篇論文提出一個六位元、每秒十億次取樣的類比/數位轉換器。此轉換器適用於光(磁)學讀取通道晶片及高速的乙太網路晶片上。採用了快閃式架構來達到高速的要求，並使用全差動的方式來提高系統的整體效能。包含了一個追蹤保持電路來消除因為時脈訊號及輸入訊號傳遞到眾多比較器所造成的取樣時間誤差，以提高其動態的表現。另外，針對數位編碼器在高速下的穩定運作，做了仔細的考量。
    　　採用了TSMC 0.18μm，1P6M的CMOS 混和信號製程，整個類比/數位轉換器的晶片面積為1.2x1.2mm2。模擬結果顯示在1-Gsample/sec的取樣頻率下，當輸入信號為496MHz 時，可以達到5.2位元的有效解析度。在1.8 伏特，1-Gsample/sec的取樣速度下消耗192mW 的功率。

    　　This thesis proposes a 6-b 1G-sample/sec A/D Converter. The converter is suitable to optical (magnetic) read-channel and high-speed Ethernet chips. The flash structure is adopted to accomplish the requirement of higher speed. Moreover, system performance is increased by using fully differential methods. These include an on-chip T/H to eliminate the sampling time skews resulted from the fact that the clock and input signal are being transmitted to numerous comparators, and further enhance the dynamic performance. In additional, there are elaborated considerations made for enabling digital encoders to be operating stably in high speed.
    　　The chip area is 1.2x1.2mm2 in TSMC 0.18μm CMOS 1P6M mixed-signal process. Simulation results show that the converter can achieve effective number of bit higher than 5.2 at the input frequency up to 496MHz and sampling frequency up to 1-Gsample/sec. The converter consumes 180mW at 1.8V when operating at 1-Gsample/sec.

    第一章 緒論 1 1.1 研究動機 1 1.2 論文架構 3 第二章 高速類比數位轉換器的架構 4 2.1 快閃式類比數位轉換器（Flash ADC） 5 2.2 兩階快閃式類比數位轉換器（Two-Step Flash ADC） 6 2.3 管線式類比數位轉換器（Pipeline ADC） 10 2.4 時間分離式類比數位轉換器（Time Interleaved ADC） 12 2.5 連續逼近式類比數位轉換器（SAR ADC） 13 2.6 折疊及內插式類比數位轉換器（Folding and Interpolating ADC） 16 第三章 快閃式類比數位轉換器之實現 20 3.1 系統架構 20 3.2 追蹤保持電路 23 3.2.1 追蹤保持電路對快閃式ADC效能的增進 22 3.2.2 追蹤保持電路的實現 23 3.3 參考電壓產生器 27 3.3.1 單端輸入及差動輸入比較器對參考電壓的影響 28 3.3.2 參考電壓緩衝器 31 3.4 前置放大器與比較器 32 3.4.1 前置放大器 33 3.4.2 比較器及SR Latch 35 3.5 編碼器 38 3.5.1 泡沫錯誤及Metastability 38 3.5.2 電路實現 39 3.5.3 True Single Phase Clocked Register (TSPCR) 45 3.6 週邊電路 47 3.6.1 偏壓電路 47 3.6.2 時脈產生器 49 第四章 佈局考量及模擬結果 50 4.1 平面配置 50 4.2 佈局考量 51 4.3 模擬結果 54 第五章 結論與未來展望 59 參考文獻 61

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