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研究生：	韋智凱 Wei, Chih-Kai
論文名稱：	嵌入式處理器之軟體方式自我測試的改良方案 Improving Software-Based Self-Testing with Multiple-Level Abstractions for Embedded Processors
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	60
中文關鍵詞：	自我測試、處理器測試
外文關鍵詞：	ARM, SOC, testing, SBST, processor
相關次數：	點閱：73 下載：4
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除了硬體BIST或者scan chain之外，以軟體方式讓處理器進行自我測試是另一種可行的方案，而且這種方法越來越受到重視。這種方法是讓處理器執行自己的指令串(測試程式)來測試處理器本身。在這篇論文中我們提出了一個新的軟體測試方案，而這方案可以產生效果好而且效率高的測試程式。其他已提出的類似方法中，大部分都使用相同的策略來測試所有種類的電路，而我們的方法較有彈性，會針對不同種類電路的特性採用最合適的方法。所以，程式的發展過程可以較簡單，而且最後得到的fault coverage可以更好。我們用一顆複雜的嵌入式處理器來評估此方案的效果，而實驗的結果也證實了這方法的可行性。

Besides hardware BIST and scan chains, software-based self-testing (SBST) is an alternative to test a processor core, and this methodology is becoming more and more popular. As implied in the name, in SBST methodology a processor executes its instruction sequences (test programs) to test itself. We introduce a novel methodology that can produce an effective and efficient test program. Unlike other software-based schemes that use a single strategy for all kinds of circuits, our methodology is more flexible that adopts different strategies for different kind of circuits. Thus, test development is easier and the attained fault coverage is higher. We evaluate the effectiveness of our methodology using a complex embedded processor, and the experimental results confirm the feasibility.

Chinese abstract………………………………………………………………………iii
Abstract…………………………………………………………………………………iv
Acknowledgement………………………………………………………………………v
List of tables…………………………………………………………………………viii
List of figures…………………………………………………………………………ix
Chapter 1 Introduction…………………………………………………………………1
1 Motivation………………………………………………………………………1
2 Introduction to the proposed methodology………………………………………2
3 Organization of the thesis…………………………………………………………4
Chapter 2 Previous works and background …………………………………………6
1 Previous works……………………………………………………………………6
2 Background: ARM microprocessors……………………………………………9
2.1 Instructions…………………………………………………………………10
2.2 Processor modes……………………………………………………………11
2.3 Registers……………………………………………………………………12
2.4 Exceptions…………………………………………………………………12
Chapter 3 Test program development………………………………………………14
1 Test architecture and environment………………………………………………14
2 Overview of our proposal………………………………………………………18
3 Test development for registers…………………………………………………19
4 Test development for computation logics………………………………………23
5 Test development for control & steering logics…………………………………37
6 Test development for pipeline mechanisms……………………………………37
6.1 Testing of control hazard detection logics…………………………………37
6.2 Testing of pipeline forwarding mechanisms………………………………39
Chapter 4 Experimental results………………………………………………………42
1 Fault simulation…………………………………………………………………42
2 Synthesis case 1: TSMC 0.35 um, 30MHz……………………………………44
3 Synthesis case 2: TSMC 0.35 um, 50MHz……………………………………45
4 Synthesis case 3: TSMC 0.18 um, 125MHz……………………………………47
5 Analyses…………………………………………………………………………48
6 Comparison with other works…………………………………………………51
7 Trial of random test program……………………………………………………52
Chapter 5 Conclusions and future works……………………………………………56
1 Conclusions……………………………………………………………………56
2 Future works……………………………………………………………………57
References………………………………………………………………………………58

                                    

1. Li Chen and S. Dey, “Software-Based Self-Testing Methodology for Processor Cores,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 3, March 2001.

2. A. Paschalis and D. Gizopoulos, “Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, January 2005.

3. F. Corno, M. Sonza Reorda, G. Squillero, and M. Violante, “On the Test of Microprocessor IP Cores,” Design, Automation and Test in Europe 2001.

4. N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-Based Self-Testing of Embedded Processor,” IEEE Transactions on Computers, vol. 54, no.4, April 2005.

5. 陳旻謙，“對於嵌入式處理器之功能性測試的混合方法”碩士論文，電機工程
研究所，國立成功大學，2003。

6. 王建章，“雙處理器架構之SoC平台”碩士論文，電機工程研究所，國立成功
大學，2004。

7. ARM Corporation, “ARM Architecture Reference Manual,” ARM DDI0100E, 2000.

8. P. Parvathala, K. Maneparambil, and W. Lindsay, “FRITS-A Microprocessor
Functional BIST Method,” International Test Conference, 2002.

9. Michael L. Bushnell and Vishwani D. Agrawal, “Essentials of Electronic Testing,” Kluwer Academic Publishers, 2000.

10. A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian, “Deterministic Software-Based Self-Testing of Embedded Processor Cores,” Design, Automation and Test in Europe 2001.

11. W. -C. Lai and K.-T. Cheng, "Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip," Design Automation Conference 2001.

12. S. Shamshiri, H. Esmaeilzadeh, and Z. Navabi, "Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores," Asian Test Symposium 2004.

13. Syntest Corporation, “TurboScan Reference Manual,” version 2.6, August 2002.

14. F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, “Fully Automatic Test Program Generation for Microprocessor Cores,” Design, Automation and Test in Europe 2003.

15. K. Batcher and C. Papachristou, “Instruction Randomization Self Test for Processor Cores,” VLSI Test Symposium 1999.

16. N. Kranitis, A. Paschalis, D. Gizopoulos, and Y. Zorian, “Effective Software Self-Test Methodology for Processor Cores,” Design, Automation and Test in Europe 2002.

17. David A. Patterson and John L. Hennessy, “Computer Organization & Design,” San Francisco, CA: Morgan Kaufmann, 1998.

18. David A. Patterson and John L. Hennessy, “Computer Architecture A Quantitative Approach,” San Francisco, CA: Morgan Kaufmann, 1996.

校內：立即公開
校外：2006-08-29公開

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