無線傳能與應用於物件偵測的諧波雷達為現今重要之技術。本論文主要為設計一可提供多物件或多人偵測之自供電式射頻標籤(Self-powered RF tag)，並結合低電壓鎖相迴路(Low voltage phase-locked loop)，在整體系統中作為感測端的應用。
本論文提出的系統架構為整合射頻標籤與鎖相迴路，未來可應用於二次諧波訊號進行人體胸腔呼吸起伏之偵測。首先輸入端利用偶極天線擷取外部傳入2.4 GHz之射頻訊號，再經由差動變壓器和全波整流器輸出DC訊號(0.6 V)作為後方雙推式注入鎖定倍頻器之電壓源，進一步放大訊號以及達成自供電之標的。在供應電壓=0.58 V時(輸入功率 = 10 dBm)，雙推注入鎖定倍頻器的輸出功率為-13.852 dBm，鎖定範圍為200 MHz，核心功耗為0.46 mW，緩衝器的功耗則為1.861 mW，相位雜訊在1 MHz位移處有-110.2 dBc/Hz的表現。最後4.796 GHz的輸出頻率再經由除頻器降頻至70.5 MHz用以做為鎖相迴路之參考頻率。
為了實現多人偵測且不互相干擾之標的，本論文將鎖相迴路之輸出頻率設計為以4.8 GHz為中心，相隔四倍之參考頻率。藉由多模組除頻器的控制位元(二位元)可達到多頻率輸出之目標，其分別為4.512 GHz、4.794 GHz、5.076 GHz。壓控振盪器採用互補式電容電感共振腔(LC-tank VCO)搭配二位元之切換電容陣列以增加可調變範圍並降低Kvco，以及提升整體系統的相位雜訊表現。相位頻率偵測器使用真單相時脈(True single-phase clock, TSPC)之架構來增加操作速度與降低功耗，同時也使用延遲鏈以減少非理想效應之影響。電荷幫浦使用改良式全N型電晶體架構，其原因除了抗製程變異佳之外，還有一額外放電路徑可降低電流不匹配，進而達到降低參考突波的效果。迴路濾波器使用二階RC濾波器，並根據設計目標來抑制不同的雜訊來源，本論文使用on-chip設計以減低非理想效應和寄生效應對整體鎖相迴路穩定度的影響。除頻器電路使用電流模式邏輯電路(Current-mode logic, CML)與Extended TSPC (E-TSPC)的架構來做為預除頻器(Prescaler)，後方使用多模組除頻器做為除頻鏈。為了滿足本論文的除數(含16、17和18)傳統的多模組除頻器必須設計四位元(16~18)，本論文使用改良式多模組除頻器，使除數只有16、17和18進而減少電晶體達到節省面積與功耗的效果。在整體鎖相迴路系統中，為了達到低電壓操作之規格(1.2 V)，本論文除了相對較為敏感的切換電容陣列壓控振盪器，均是使用Low threshold voltage (Low-Vth)之電晶體元件來設計。
上述所有的積體電路設計皆使用台積電所提供之TSMC 0.18um CMOS製程實現，本論文將依序詳細介紹射頻標籤、鎖相迴路等功能方塊之電路架構以及模擬和量測結果。

In this thesis, the circuits are fabricated by TSMC’s 180nm 1P6M CMOS process. In this thesis, a self-powered RF tag and a low-voltage phase-locked loop (PLL) are designed for multi-object detection application. The RF tag is composed of a differential transformer, a full-wave rectifier, a push-push injection-locked frequency doubler. This thesis also introduces the challenges for self-powered, voltage supply for frequency doubler is from RF input signal through the full-wave rectifier. To reduce input power request, a low operation voltage frequency doubler must be implemented. Therefore, minimum voltage supply is 0.58 V for frequency doubler in our design, and the output power of the doubler can deliver -13.852 dBm. The core power consumption for frequency doubler is only 0.46mW in 4.8GHz output frequency, and the phase noise is -110.2 dBc/Hz at 1 MHz frequency offset.

The second part of this thesis is PLL, which consists of a phase frequency detector (PFD), charge pump (CP), a second order loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. There are three selectable output frequencies, which are 4.512 GHz, 4.794 GHz, 5.076 GHz for PLL by controlling divider ratio with 64, 68or 72. A two bits switch capacitor array is implemented in VCO for pursuing a wider tuning range but not increasing Kvco simultaneously. The spur level is -43.278 dBc and the phase noise is -118.857 dBc/Hz at 1 MHz frequency offset. By using a 1.2 V supply voltage, total power consumption without buffers is 9.823 mW.

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