隨著半導體製程的進步，單晶片系統的設計愈來愈複雜，要如何有效率地對一個單晶片系統進行測試與除錯，已經成為一個必須處理的問題。一個具備測試與除錯能力的整合平台在過去被提出來處理此問題。此平台可支援多種測試與除錯的方法，測試方法包含了電路的掃描測試與記憶體內建自我測試等方法。除錯方法包含了以時脈中斷點為條件，以事件觸發機制的除錯功能與以交互觸發為基礎的軟硬體共同除錯機制。
在本篇論文中，我們提出了一套自動化系統—DASTEP2。透過此自動化系統，使用者可以快速地建立一個測試與除錯整合平台並整合矽智財電路至此平台上，以處理單晶片系統(SoC)的測試與除錯問題。DASTEP2提供對矽智財電路包覆符合IEEE 1500 標準之包裹，產生記憶體自我測試(Memory BIST)架構，進行測試排程，產生測試存取機制與相對應的測試匯流排等功能。除了自動化設計流程，此系統亦提供了一套完整的驗證流程，可供使用者驗證由自動化設計流程所產生的測試與除錯整合平台。DASTEP2亦提供一套測試與除錯工具，幫助使用者在IC或是在FPGA上執行整個測試與除錯流程。在這套自動化系統中，我們也提供了一個完整的整合開發環境，使用者僅需透過簡單的操作，即可使用上述的功能。此套系統已被實際應用於一個單晶片開發流程中，並產出一個具備測試與除錯功能的實體晶片。綜合以上所述，DASTEP2能實際整合一個具備測試與除錯功能的單晶片系統，幫助使用者處理單晶片系統測試與除錯的問題。

To deal with the testing and debugging problems of an SoC, an SoC test and debug platform has been developed previously. This platform provides many useful techniques to help the user validate an SoC efficiently. In this thesis, a design automation system, called DASTEP2, is presented. This automation system can help the user build an SoC test and debug platform efficiently. Therefore, the time of testing and debugging integration can be greatly reduced. DASTEP2 can modify digital IP cores into testable one and wrap it with the IEEE 1500 wrappers. For the memory modules, a low-cost memory built-in self-test (BIST) architecture can be generated automatically. In addition, a test-access-mechanism (TAM) controller along with the corresponding test bus can be automatically synthesized. To verify the constructed platform, DASTEP2 provides a verification flow. A simulation environment is generated to simulate and verify entire test procedure. To support manufacturing testing and post-silicon debugging, a set of tools for testing and debugging are developed to enable and facilitate the testing and debugging procedures on real chips or during FPGA prototyping. Consequently, the user can validate the SoC efficiently. All the functionality of DASTEP2 can be accessed by a friendly graphic user interface, which makes DASTEP2 an easy-to-use SoC test and debug integration tool. DASTEP2 has been applied to an SoC case. The chip has been fabricated. The measurement results show that our approach is efficient and effective for SoC test and debug.

[1]Y.-C. Hsu, F. Tsai, W. Jong, and Y.-T. Chang, "Visibility enhancement for silicon debug," in Design Automation Conference, 2006 43rd ACM/IEEE, 2006, pp. 13-18.
[2]B. Vermeulen, "Functional Debug Techniques for Embedded Systems," Design & Test of Computers, IEEE, vol. 25, pp. 208-215, 2008.
[3]M. H. Tehranipour, M. Nourani, S. M. Fakhraie, and A. Afzali-Kusha, "Systematic test program generation for SoC testing using embedded processor," in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, pp. V-541-V-544 vol.5.
[4]M. Benabdenbi, A. Greiner, F. Pecheux, E. Viaud, and M. Tuna, "STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores," in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, pp. 712-713 Vol.1.
[5]A. Krstic, W.-C. Lai, K.-T. Cheng, L. Chen, and S. Dey, "Embedded software-based self-test for programmable core-based designs," Design & Test of Computers, IEEE, vol. 19, pp. 18-27, 2002.
[6]J.-R. Huang, M. K. Iyer, and K.-T. Cheng, "A self-test methodology for IP cores in bus-based programmable SoCs," in VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001, 2001, pp. 198-203.
[7]M. Grosso, W. J. Perez H, D. Ravotto, E. Sanchez, M. S. Reorda, and J. V. Medina, "A software-based self-test methodology for system peripherals," in Test Symposium (ETS), 2010 15th IEEE European, 2010, pp. 195-200.
[8]"IEEE Standard Testability Method for Embedded Core-based Integrated Circuits," in IEEE Std 1500-2005, ed, 2012.
[9]B. Vermeulen and S. K. Goel, "Design for debug: catching design errors in digital chips," Design & Test of Computers, IEEE, vol. 19, pp. 35-43, 2002.
[10]L.-B. Chen, Y.-C. Liu, C.-H. Chen, C.-F. Kao, and I.-J. Huang, "Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor," in Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific, 2008, pp. 117-118.
[11]I.-J. Huang, C.-F. Kao, H.-M. Chen, C.-N. Juan, and T.-A. Lu, "A retargetable embedded in-circuit emulation module for microprocessors," Design & Test of Computers, IEEE, vol. 19, pp. 28-38, 2002.
[12]M. Abramovici, "In-System Silicon Validation and Debug," Design & Test of Computers, IEEE, vol. 25, pp. 216-223, 2008.
[13]H. F. Ko, A. B. Kinsman, and N. Nicolici, "Design-for-Debug Architecture for Distributed Embedded Logic Analysis," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1380-1393, 2011.
[14]L. Xiao and X. Qiang, "On Multiplexed Signal Tracing for Post-Silicon Validation," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 32, pp. 748-759, 2013.
[15]F.-C. Yang, Y.-T. Lin, C.-F. Kao, and I.-J. Huang, "An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 571-584, 2011.
[16] CoreSightTM Components Techinical Reference Manual. Available: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/DDI0314H_coresight_components_trm.pdf
[17]B. Vermeulen and S. Bakker, "Debug architecture for the En-II system chip," Computers & Digital Techniques, IET, vol. 1, pp. 678-684, 2007.
[18]K.-J. Lee, C.-Y. Chang, A. Su, and S.-Y. Liang, "A unified test and debug platform for SOC design," in ASIC, 2009. ASICON '09. IEEE 8th International Conference on, 2009, pp. 577-580.
[19]J.-W. Jhou, "Inside-Core Event-Trigger Mechanism for SoC Silicon Debugging," M.S. Thesis, Department of Electrical Engineering, Nation Cheng Kung University.
[20]K.-J. Lee, S. A., L.-F. Chen, J.-W. Jhou, K. J., and L. M., "A software/hardware co-debug platform for multi-core systems," in ASIC (ASICON), 2011 IEEE 9th International Conference on, 2011, pp. 259-262.
[21]K.-J. Lee, T.-Y. Hsieh, C.-Y. Chang, Y.-T. Hong, and W.-C. Huang, "On-Chip SOC Test Platform Design Based on IEEE 1500 Standard," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, pp. 1134-1139, 2010.
[22]L.-T. Wang, R. Apte, S. Wu, B. Sheu, W.-B. Jone, J. Guo, K.-J. Lee, W.-S. Wang, X. Wen, H.-J. Chao, J. Liu, Y. Niu, Y.-C. Sung, C.-C. Wang, and F. Li, "Turbo1500: Core-Based Design for Test and Diagnosis," Design & Test of Computers, IEEE, vol. 26, pp. 26-35, 2009.
[23]C.-Y. Lo, C.-H. Wang, K.-L. Cheng, J.-R. Huang, C.-W. Wang, S.-M. Wang, and C.-W. Wu, "STEAC: A Platform for Automatic SOC Test Integration," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 15, pp. 541-545, 2007.
[24]C.-C. Chi, C.-Y. Lo, T.-W. Ko, and C.-W. Wu, "Test Integration for SOC Supporting Very Low-Cost Testers," in Asian Test Symposium, 2009. ATS '09., 2009, pp. 287-292.
[25]W.-C. Huang, C.-Y. Chang, and K.-J. Lee, "Toward Automatic Synthesis of SOC Test Platforms," in VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on, 2007, pp. 1-4.
[26]Cadence. Available: http://www.cadence.com/us/pages/default.aspx
[27]K. Goossens, B. Vermeulen, and A. B. Nejad, "A high-level debug environment for communication-centric debug," in Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., 2009, pp. 202-207.
[28]The GTK+ Project. Available: http://www.gtk.org/
[29]S.-C. Shen, "A Low Cost Memory Built-in Self-Test Architecture and its Design Automation," M.S. Thesis, Department of Electrical Engineering, Nation Cheng Kung University.
[30]FTDI on-line docmentation. Available: http://www.ftdichip.com/Support/FTDocuments.htm
[31]"IEEE Standard Verilog Hardware Description Language," in IEEE Std 1364-2001, ed, 2001.