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研究生：	翁孟澤 Weng, Meng-Tse
論文名稱：	應用於S/PDIF音頻接收器的4.096-24.576Mb/s時脈與資料回復電路和解碼器之設計 Design of a 4.096-24.576Mb/s Clock and Data Recovery Circuit and a Decoder for S/PDIF Audio Receiver
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	105
中文關鍵詞：	音頻接收器、時脈與資料回復電路
外文關鍵詞：	Audio Receiver, Clock and Data Recovery (CDR)
相關次數：	點閱：116 下載：4
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在大多數的音頻系統中，音頻接收器是一個必要的一個產品，它包含兩個主要基本的元件去處理音頻訊號，一個是前端的時脈與資料回復電路，另一個則是後端的解碼器。前端的時脈與資料回復電路是用來萃取以及回復輸入資料裡的正確時脈和資料，而後端的解碼器則是用來對前端時脈與資料回復電路所產生的回復資料做解碼，且將回復資料的位元流解碼成立體聲的音訊流或是5.1聲道的音訊流，然後喇叭或耳機根據這些音訊流而播放出聲音或音樂來。除此之外，為了提高在傳輸過程當中的抗雜訊的能力，音頻收發機採用數位介面(如S/PDIF)來收發資料。
在本篇論文裡將提出一個可以滿足所有S/PDIF應用的連續速率時脈和資料回復電路架構，所提出的時脈與資料回復電路架構是加入一個額外的迴路到傳統的時脈與資料回復電路上，如此可支援寬廣且連續的資料傳輸率(128倍的取樣頻率)範圍，範圍從4.096Mb/s到24.576Mb/s，且它能在沒有使用參考時脈和微控制器的情況下，達到自動頻率校正的功能，另外，此時脈與資料回復電路由於有這樣子的電路架構而能大大地提升其整體效能。這個時脈與資料回復電路是用台灣積體電路製造股份有限公司所提供的0.35μm 2P4M混合訊號互補式金氧半製程來製造，它的整體面積大約為1.73mm2，在所有可操作的輸入資料傳輸率裡，其輸出時脈的均方根抖動和峰對峰抖動全都分別小於13.53ps和91ps，且在接收隨機的S/PDIF資料，其所有量測的誤碼率皆能小於10-10，而在電源3.3V的情況下去接收25Mb/s的資料，其功率消耗為最大，大小為10.79mW。
除了前端的時脈與資料回復電路外，在本篇論文裡所設計的後端的解碼器則是可以提供九種不同且都能滿足序列音頻介面格式的輸出模式，且這個解碼器還可以自動偵測出輸入資料傳輸率的改變並要求前端的時脈與資料回復電路重新去處理新的資料傳輸率。另外，此解碼器燒錄在Alter FLEX10KE模擬板上，藉此來模擬及驗證其功能。

An audio receiver is essential in mostly audio systems. It has two fundamental components to cope with audio signals. One is a front-end clock and data recovery (CDR) circuit and the other is a back-end decoder. The frond-end CDR circuit is used to extract the clock and retime the data from the input data. The back-end decoder is used to decode the bitstreams of the retimed data generated by the font-end CDR circuit into stereo audio streams or 5.1-channel audio streams. Then speakers or headphones play sound or music according to these audio streams. Moreover, digital interfaces such as S/PDIF are adopted in audio transceivers in order to improve the anti-noise capability of an audio signal during transmission.
In this thesis, a continuous-rate CDR architecture satisfying all S/PDIF audio applications is proposed. The proposed CDR architecture adds an extra loop into the traditional CDR circuit to support a wide and continuous range of data rates, 128 times sampling frequencies, from 4.096Mb/s to 24.576Mb/s. It can also achieve the frequency acquisition automatically without the reference clock or the microcontroller. The whole performance of the CDR circuit can be enhanced greatly due to its architecture. The CDR circuit has been fabricated in a TSMC 0.35μm 2P4M mixed signal CMOS process. Its total area is about 1.73mm2. The measured root-mean-square jitters and the measured peak-to- peak jitters of output clocks are all under 13.53ps and 91ps respectively over all the input data rates. All measured bit error rates are less than 10-10 for a random S/PDIF data. The maximum power consumption is 10.79mW from a 3.3V supply when receiving a 25Mb/s S/PDIF data.
In addition to the font-end CDR circuit, the back-end decoder designed in this thesis can provide nine different output modes satisfying the serial audio interface formats. This decoder can also automatically detect a change in the input data rate and demand that the front-end CDR circuit reacquire the new data rate. The decoder is burned into the Alter FLEX10KE emulation board for emulation and verification.

Abstract (Chinese)				i
Abstract (English)				ii
Acknowledgments  				iv
Table of Contents				v
List of Tables	       			viii
List of Figures	        			ix
	
1. Introduction	        			1
   1.1 Overview 				1
   1.2 Background       			1
   1.3 Motivation  			2
   1.4 S/PDIF Audio Systems 		3
   1.5 Thesis organization			6
		
2. System Design of Clock and Data Recovery	7
   2.1 Overview				7
   2.2 Design Target			7
   2.3 CDR Fundamentals			8
       2.3.1 Phase Detector			10
       2.3.2 Frequency Detector		12
       2.3.3 Charge Pump			14
       2.3.4 Loop Filter			14
       2.3.5 Voltage-Controlled Oscillator	15
       2.3.6 Divide-by-N Divider		16
   2.4 Proposed CDR Architecture 		16
   2.5 Linear Model Analysis		19
   2.6 Stability Analysis			24
   2.7 Noise Analysis			28
   2.8 Behavior Model and Simulation		35
		
3. Circuit Design of Clock and Data Recovery	38
   3.1 Overview				38
   3.2 Transition Counter			38
   3.3 Digital Coarse Tuning Block		39
   3.4 Frequency Detector			40
   3.5 Phase Detector			42
   3.6 Divider 				44
   3.7 Buffers				44
   3.8 Charge Pump				45
   3.9 Loop Filter				48
   3.10 Control Voltage Generator		48
   3.11 Voltage-Controlled Oscillator	53
        3.11.1 Bias Generator Circuit	54
        3.11.2 Delay Cell			56
        3.11.3 Differential-to-Differential Circuit 58
   3.12 Whole Chip Simulation		58
		
4. Decoder Design				66
   4.1 Overview				66
   4.2 Serial Audio Interface Formats	66
       4.2.1 Inter-IC Sound Mode (I2S Mode)	66
       4.2.2 Left-Justified Mode		67
       4.2.3 Right-Justified Mode		68
   4.3 Design Flow				68
       4.3.1 Functional Specification 	69
       4.3.2 Architecture Design		71
       4.3.3 RTL Code Design		72
       4.3.4 Synthesis			72
       4.3.5 Altera FLEX10KE Emulation Board 	72
   4.4 Simulation Results			72
		
5. Measurement				77
   5.1 Overview				77
   5.2 CDR Circuit				77
       5.2.1 CDR Chip			77
       5.2.2 Measurement Setup 		79
       5.2.3 Experimental Results		80
   5.3 Decoder 				85
       5.3.1 Measurement Setup		85
       5.3.2 Experimental Results 		86
   5.4 Audio Receiver 			92
       5.4.1 Measurement Setup		92
       5.4.2 Experimental Results		92
       		
6. Conclusions				101
		
References	                           102

                                    

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校內：2009-06-20公開
校外：2009-06-20公開

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