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研究生： 胡灯嬛
Hu, Deng-Huan
論文名稱： 低電壓且具有創新自我時序觸發技術的感應放大器之可容忍製程變異的靜態隨機存取記憶
Variation-Insensitive Low-Voltage SRAM using Novel Self-timing Activation Techniques for Sense Amplifiers
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 65
中文關鍵詞： 自我時序觸發 、製程 、靜態隨機存取記憶體
外文關鍵詞： Process variation, SRAM, Self-timing activation
相關次數： 點閱：56  下載：1 
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    • 在這篇論文中，我們提出針對靜態隨機存取記憶體的自我時序的兩種創新容忍度技術。一個是位元線感應自我觸發結構，另一個為N型電晶體延遲串。感應放大器可以被位元線感應自我觸發結構或是N型電晶體延遲串觸發其取決於對於晶片上的變異和效能限制的明智判斷。針對高負載的位元線一個低振幅的技術也在其中被提出去支援位元線感應自我觸發結構。在低電壓下，隨機存取記憶體胞被設計去自然的維持位元線電壓不會低於電晶體的飽和電壓。在高電壓時，位元線的電壓振幅可以被完成訊號或是N型電晶體延遲串限制住。當晶圓內的變異對先進製程是關鍵時，近來大部分對於自我時序電路的技術卻仍專注在晶圓間的變異。同時考量晶圓間和晶圓內的變異且在使用90nm製程下，使用提出的架構比起傳統的架構將使得讀取錯誤的機率減少20%。這個創新的自我時序觸發技術同時支援靜態隨機存取記憶體操作在 1伏特到0.2伏特這樣一個廣的電壓範圍。

    In this thesis, two novel tolerant techniques for SRAM self-timing are presented. One of the techniques is self-activated bit-line sensing scheme (SABLS) and the other is NMOS delay chain (NDC). The sense amplifier (SA) can be either triggered by SABLS or NDC with intelligent decisions depending on on-chip variations and performance constraints. A low-swing technique for heavy-loading bit-lines is also proposed herein to support SABLS activation. The SRAM cells are designed to keep the bit-line voltage no less than VSAT spontaneously in low voltages. When in high voltages, the swing voltage of bit-line can be limited by completed signal or turning on NDC instead. Most of recent techniques may only focus on inter-die variation in their self-timing circuits, while intra-die variation is critical in the advanced technologies. Using the proposed schemes, the access failure rate will reduce 20 % compared with conventional schemes in 90nm considering both inter-die and intra-die variations. The novel self-timing activation techniques can also enables SRAM operating in a wide range of supply voltage from 1 V to 0.2V.

    Chapter 1 Introduction 1 1.1 Preliminary 1 1.2 Motivation 7 1.3 Contributions 7 1.4 Thesis Organization 8 Chapter 2 Design of Low voltage SRAMs under Process Variation 9 2.1 Process Variation in SRAM and SA 9 2.1.1 Process Variation in SRAM Cell 11 2.1.2 Process Variation in SA 16 2.2 SRAM Cell in Low Voltage 18 2.3 Proposed SRAM Cell and SA in Our SRAM 21 2.4 Failures in the Proposed 13T SRAM Cell 23 2.5 Summary 24 Chapter 3 SA Activation Signal Generators under Process Variation 26 3.1 Conventional- Inverter Delay chain 26 3.2 Variably Delay 28 3.3 Replica Technique 29 3.4 BIST-Assisted Timing Tracking 31 3.5 Summary 33 Chapter 4 Proposed Self-timing Activation Techniques 34 4.1 Self-timing Activation Techniques for Increasing Access Failure Tolerance 34 4.1.1 Self-Activated Bit-Line Sensing Scheme (SABLS) 34 4.1.2 NMOS Delay Chain (NDC) 36 4.2 Low Bit-Line Swing Technologies 37 4.2.1 Turn Off the Discharge Path as Soon as Possible 37 4.2.2 Bit-Line Voltage Clamping Technique 39 Chapter 5 Simulation Results 40 5.1 Configuration of Simulation Circuits and Environment 40 5.2 Delay Variation of Bit-Line Discharge and SA Activation Signal 42 5.3 Access Failure Tolerance Simulation 44 5.4 Bit-Line Swing Simulation 50 5.5 Read latency time 52 5.6 Layout and Chip Implementation 55 5.7 Summary 58 Chapter 6 Conclusions and Future Work 59 6.1 Conclusions 59 6.2 Future work 60 Reference 61

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