本論文所研究的元件為陣列式暫態電壓抑制器(Transient Voltage Suppresspr, TVS)，陣列式暫態電壓抑制器是當今對於靜電防護元件的發展主流。使用MicroSim PSpice軟體模擬IEC61000-4-2規範與傳輸線脈衝(Transmission Line Pulse, TLP)的放電波形對陣列式暫態電壓抑制器進行模擬分析，經由PSpice的模擬結果觀察與分析在靜電放電( Electro Static Discharge, ESD)時對暫態電壓抑制器的電性變化。本文採用陣列式暫態電壓抑制器元件進行軟體模擬，經由模擬軟體分析當陣列式暫態電壓抑制器與電源連接時靜電放電將會影響電源電壓產生浮動。最後經由實際投片於晶圓廠並封裝在SOT-236包裝內，經由實際測試本文所設計的陣列式暫態電壓抑制器具有承受IEC61000-4-2規範等級四以上的能力，能夠承受接觸放電高達±18kV。並且因陣列式暫態電壓抑制器內部結構將靜電放電的電流路徑與電源進行隔離，經由實際進行測試，本文陣列式暫態電壓抑制器能夠有效抑制靜電放電衝擊時所產生的電源電壓浮動現象。

The research topic of this thesis is about the Transient Voltage Suppressor Array (TVS). A simulation based on the MicroSim PSpice software to analysis the changes of Electro Static Discharge (ESD) voltage will be carried out. The simulation method is defined by IEC61000-4-2 specification. In this thesis, a TVS device structure is use to simulate the floating when TVS was connected to voltage source or signal source. Then the TVS design is provided to the wafer fabrication for manufacturing, the finish die will then be assembled in a SOT-236 package. The ESD protection capability under IEC61000-4-2 contact model specification of this TVS device is above ±18kV which comply with the IEC61000-4-2 level4 degree. In addition, the path of ESD current was separated from the path of signal source current by the TVS structure. The result of the simulation and measurement shows that this TVS structure is feasible and effective to reduce the float of input ESD voltage.

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