近年來消費者對於顯示器畫面品質的要求不斷提升，由於主動式矩陣有機發光二極體顯示器具有廣視角、快速反應時間、自發光以及可撓曲特性等優點，使其被廣泛應用於許多消費性電子產品。低溫多晶矽薄膜電晶體因具有優越的電流驅動能力，常被用來製作主動式矩陣有機發光二極體顯示器之背板進而縮減畫素電路之佈局面積，然而其臨界電壓變異將影響畫素電路電流的穩定度並造成畫面品質下降。另一方面，閃爍現象於主動式矩陣有機發光二極體顯示器會造成對比度下降且增加額外功率消耗。除此之外，應用於智慧手錶時，為了降低功率消耗，將採用低畫面更新頻率方法以節省顯示器之功耗，然而此方法會大幅延長發光時間，造成驅動電晶體閘極端電壓因開關電晶體的漏電現象使驅動電壓不易維持進而影響畫面品質。此外，高解析度主動式矩陣液晶顯示器由於畫素的增加導致掃描線上的高負載，造成採用傳統架構的氫化非晶矽閘極驅動電路之輸出波形的上升時間及下降時間過長，使畫素電路無法正確寫入資料電壓。
針對上述問題，本論文提出兩個以低溫多晶矽薄膜電晶體設計並具備防漏電架構之畫素補償電路以及一個以氫化非晶矽薄膜電晶體設計並具備較高驅動能力之閘極驅動電路，並透過模擬軟體驗證所提出電路之可行性。第一個電路為適用於低畫面更新頻率顯示器並利用額外的電容防止漏電流之畫素電路，其電路架構由九顆電晶體與兩顆電容所組成，特色為利用額外的電容儲存與驅動電晶體閘極端相同之電壓，使開關電晶體之漏電流最小化，藉此抑制驅動電晶體閘極端電壓變異。根據模擬結果，當驅動電晶體的臨界電壓變異±0.5 V時，其相對電流誤差率皆小於4.61%。第二個電路為結合漏電流補償架構並應用於智慧手錶之畫素電路，其電路架構由八顆電晶體與一顆電容所組成，特色為利用一開關電晶體提供補償電流，使驅動電晶體閘極端電壓不受開關電晶體漏電影響，確保驅動電晶體提供穩定電流並維持高畫面品質。透過模擬證明，當驅動電晶體的臨界電壓變異±0.5 V時，其相對電流誤差率皆小於4.5%。第三個電路為使用電壓抬升架構以改善輸出波形下降時間之閘極驅動電路，其電路架構由十一顆電晶體與三顆電容所組成，特色為驅動電晶體的閘極端電壓被抬升至更高的電壓準位，因此不需要增加驅動電晶體的元件尺寸，就能改善輸出波形的下降時間，模擬結果顯示其輸出波形之下降時間可由1.326 µs改善為1.062 µs。

In recent years, consumers’ demands on the image quality of displays make active matrix organic light-emitting diodes (AMOLEDs) be widely utilized in consumers’ electronic products owing to the advantages of AMOLED displays, such as wide viewing angle, fast response time, self-emission, and flexibility. The low-temperature polycrystalline thin-film transistor is usually used to fabricate the backplane of the AMOLED displays to reduce the layout area of the pixel circuits because of its superior current driving capability. However, the threshold voltage variation of LTPS TFTs results in the non-uniformity of OLED current, decreasing the image quality of displays. Furthermore, the flicker phenomenon of AMOLED displays decreases the contrast ratio and increases the additional power consumption of displays. Nevertheless, when applied to smartwatches, the method of low-frame-rates will be used to achieve low power consumption. However, this method greatly prolongs the emission time, leading to the voltage at the gate node of the driving TFT to maintain difficultly due to the leakage current of the switching TFTs. Thus, the voltage at the gate node of the driving TFT is extremely distorted, decreasing the image uniformity of displays. In addition, with regard to high-resolution AMOLED displays, the numerous pixels cause high loading on the scan line, resulting in the increase of the rising time and falling time of output waveforms generated by the hydrogenated amorphous silicon (a-Si:H) gate driver circuit using the conventional scheme, causing the pixel circuit to program the data voltage incorrectly.
This thesis proposes two LTPS pixel circuits with a leakage current compensation structure and one a-Si:H gate driver circuit with enhanced driving capability, and the feasibility of the proposed circuits is verified by the HSPICE simulation software. The first LTPS compensation pixel circuit using an additional capacitor to prevent the leakage current of LTPS TFTs is suitable for low-frame-rate displays. The proposed pixel circuit is composed of nine TFTs and two capacitors, and utilizes an additional capacitor to store the same voltage as the voltage at the gate node of the driving TFT which minimizes the leakage current of switching TFTs, suppressing the variation of the voltage at the gate node of the driving TFT. Simulation results indicate that the relative current error rates are suppressed below 4.61% as the VTH of the driving TFT varies ±0.5 V. The second LTPS pixel circuit integrates a leakage current compensation structure applied to smartwatches. The proposed pixel circuit is composed of eight TFTs and one capacitor, and uses a switching TFT to provide compensation current to the gate node of the driving TFT, thus the voltage at the gate node of the driving TFT is not affected by the leakage current of switching TFTs, ensuring that the driving TFT provides stable current and maintains high-quality images. According to simulation results, as the VTH of the driving TFT varies ±0.5 V, the relative current error rates are suppressed below 4.5%. The a-Si:H gate driver circuit uses a bootstrapping structure to improve the falling time of output waveforms. The proposed circuit is composed of eleven TFTs and three capacitors, and the voltage at the gate node of the driving TFT is bootstrapped to high level voltage, so the falling time of the output waveforms can be improved without increasing the size of the driving TFT. Simulation results show that the falling time of the output waveform is reduced from 1.326 µs to 1.062 µs.

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