隨著積體電路在設計與製程的快速發展，整合至系統單晶片的電路越來越多，負責這些電路間彼此溝通的聯絡單元(interconnection)將變得越來越重要。然而，傳統匯流排(bus)的溝通方式無法滿足於擴展性(scalability)、重複利用性(reusability)，且操作頻率會嚴重受制於實體拉線的影響。因此，網路單晶片便被提出來解決上述在單晶片溝通上受限的問題。
負責IP (Intellectual Property)與網路晶片間溝通之網路介面(network interface)，在整體網路單晶片的效能上扮演一個重要的角色。並且，採用像是AXI或OCP之標準化介面協定，將可減少在系統單晶片上的設計時間、設計風險與製造成本。但由於這些標準化介面所具有的依序限制(ordering restriction)，在沒有合適機制下，會使得進行多個記憶體存取時發生死結現象(deadlock)。在這篇論文中，我們將提出一個支援管線傳輸(pipeline)與多筆平行運算(out-of-order)之高效能資料傳輸，並且提出一種有效利用緩衝器的重新排序機制使得死結現象不會發生。實驗結果顯示，比起不使用任何緩衝器的機制，平均而言將可使整體系統效能最高提升五十六個百分比。

As the number of the integrated cores in Sys-tem-on-Chip (SoC) increases, the role of the interconnection becomes more and more important. However, the traditional buses suffer from the scalability, the reusability, and the limitation of maximum frequency. Thus, the Network-on-Chip (NoC) is proposed to solve the bottle-neck of parallel on-chip communication. The interface between an interconnection network and an IP core can often be a major factor in the performance of the inter-connection network. Moreover, standard interface proto-cols, such as AXI and OCP, reduce design time, design risk, and manufacture cost for SoC designs. However, parallel memory accesses with the ordering restriction of the interfaces will cause the deadlock situation without the proper measure. We present an efficient on-chip net-work interface for standard interface protocols, and it supports the pipelined transfer and the out-of-order functionality , both of which are the high performance transfer . We propose a reordering mechanism to guarantee deadlock-free with efficient buffer utilization. Experiments show a performance increase of up to 56% over the mechanism without the reorder buffer.

[1] International Technology Roadmap for Semiconductors. Available: http://www.itrs.net
[2] W. Huang, et al., "Many-core design from a thermal perspective," presented at the Proceedings of the 45th annual Design Automation Conference, Anaheim, California, 2008.
[3] P. Magarshack and P. G. Paulin, "System-on-chip beyond the nanometer wall," in Design Automation Conference, 2003. Proceedings, 2003, pp. 419-424.
[4] T. Bjerregaard and S. Mahadevan, "A survey of research and practices of Network-on-chip," ACM Comput. Surv., vol. 38, p. 1, 2006.
[5] H. G. Lee, et al., "On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches," ACM Trans. Des. Autom. Electron. Syst., vol. 12, pp. 1-20, 2008.
[6] ARM, "AMBA® AXI Protocol Specification," ed, 2004.
[7] OCP-IP, "Open Core Protocol Specification," ed. http://www.ocpip.org/: OCP-IP Association.
[8] K. Woo-Cheol, et al., "A practical approach of memory access parallelization to exploit multiple off-chip DDR memories," in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 447-452.
[9] S. Vangal, et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS," in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 2007, pp. 98-589.
[10] T. Bjerregaard and S. Mahadevan, "A survey of research and practices of Network-on-chip," ACM Computing Surveys, vol. 38, pp. 1-es, 2006.
[11] Network on Chip Architectures. Available: http://www.diee.unica.it/eolab2/NoC.html
[12] S. Jun and B. T. Davis, "A Burst Scheduling Access Reordering Mechanism," in International Symposium on High Performance Computer Architecture, 2007, 2007, pp. 285-294.
[13] ARM, "PrimeCell® AXI Configurable Interconnect (PL300)," ed.
[14] Y. Xu, et al., "NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing," in ASIC, 2007. ASICON '07. 7th International Conference on, 2007, pp. 890-893.
[15] B. A. A. Zitouni and R. Tourki, "Design and implementation of network interface compatible OCP For packet based NOC," in Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, 2010, pp. 1-8.
[16] Wormhole switching. Available: http://en.wikipedia.org/wiki/Wormhole_switching
[17] E. Salminen, et al., "Survey of NoC Proposals White Paper," 2008.
[18] "The Accurate Dynamic Random-Access Memory Model (ADM) package ".
[19] O. S. Initiative, SystemC v.2.0 Specification.
[20] C. Ge-Ming, "The odd-even turn model for adaptive routing," Parallel and Distributed Systems, IEEE Transactions on, vol. 11, pp. 729-738, 2000.
[21] N. McKeown, "The iSLIP scheduling algorithm for input-queued switches," Networking, IEEE/ACM Transactions on, vol. 7, pp. 188-201, 1999.
[22] K. Srinivasan and E. Salminen, "A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoC."
[23] Synopsys Ltd. Web Site. Available: http://www.synopsys.com
[24] G. H. Loh, "3D-Stacked Memory Architectures for Multi-core Processors," pp. 453-464, 2008.