本論文主要針對平行多核處理器架構研究，首先分析由SystemVerilog所建立的多層級計算架構(Multi-Level Computing Architecture ,MLCA)，深入了解上層任務層級平行的控制處理器(Control Processor,CP)執行行為後，設計下層處理器單元(Processing Unit, PU)與周邊記憶體，實現MLCA平行多核架構； MLCA上層CP負責在執行時分析及記錄任務之間的相依關係，將就緒的任務分配給底層PUs平行執行並將執行結果回傳給CP記錄。
再來針對此系統做了三種不同的實驗，實驗則以多層級計算架構MLCA多核架構執行不同的任務程式來做測試，其中包含內積、快速傅立葉轉換和八個皇后實驗，我們分析三種任務測試程式的執行行為並驗證MLCA中處理器單元執行結果的正確性。
最後分別對三個實驗做總結與分析討論，再綜合討論因為這三種實驗對我們MLCA系統所得到的心得。

This thesis focuses on the research of parallel multi-core processor architecture. Firstly, it analyzes the Multi-Level Computing Architecture (MLCA) which is established by SystemVerilog, and deeply understands the execution behavior of the parallel control processor (CP) of the upper task level. After that, the lower processing unit (PU) and the peripheral memory are designed to implement the MLCA parallel multi-core architecture; the upper layer CP of the MLCA is responsible for analyzing and recording the dependencies between tasks during execution, and assigning the ready tasks to the parallel PUs. Execute and pass the execution result back to the CP record.
Three different experiments were performed for this system. The experiment was performed with a multi-level computing architecture MLCA multi-core architecture to perform different task programs, including inner product, fast Fourier transform and eight queen experiments. We analyzed three task tests. The execution behavior of the program and verify the correctness of the execution results of the processor unit in the MLCA.
Finally, summarize and analyze the three experiments separately, and then discuss them comprehensively because of the experience gained by these three experiments on our MLCA system.

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