近年來，在無線通訊發展快速的情下，一個手機中同時擁有通訊和網路的功能己經是無可必免的趨勢，發展系統封裝(SOP)或系統單一晶片(SOC)己經是目前的主流，而結合GSM和WLAN的雙頻帶收發機已經獲得高度的關注。對於此類的收發機，若使用直接轉頻的架構，則我們會需要有操作在不同頻帶的低雜訊放大器，分別來放大從天線接收下來的GSM及WLAN的信號，而最直接的整合方式則是整合兩顆分別為GSM和WLAN的低雜訊放大電路。然而晶圓面積的消耗將會導致成本的增加，為了成本上的考量，發展單顆並能達到GSM和WLAN多標準操作頻帶的重要性已日益增加。
在本篇論文中研製兩個可同時達到GSM和WLAN標準的LNA，利用可切換式電感的結構來提供GSM和WLAN的頻帶切換，並利用fold-cascode的方式來達到低電壓的優點。本研究是以TSMC 0.18μm 1P6M RF-CMOS製程所製作。在LNA1中所模擬得到的順向增益(S21)分別為+13.347dB(GSM)及+11.324dB (WLAN)，逆向隔離(S12)分別都在-40dB以下，輸入匹配(S11)分別為-13dB及-20dB，而雜訊指數(NF)約為2.9 dB及3.4 dB，IIP3則分別在-6dBm (GSM)及-1dBm (WLAN)，消耗功率皆為8.23mW。而LNA2則是為了能使未來的Mixer電路在設計輸入阻抗匹配時，不會影響到LNA1所設計的操作頻率，因此在LNA1中增加了Buffer的設計，而LNA2中所模擬得到的順向增益(S21)分別為+10.893 dB (GSM) 及+10.673 dB (WLAN)，逆向隔離(S12)分別都在-60dB以下，輸入匹配(S11)分別為-13 dB (GSM)及-17 dB (WLAN)，而雜訊指數約為3.0 dB (GSM)及3.2 dB (GSM)，IIP3則分
別在-7.2 dBm (GSM)及-5.2 dBm (WLAN)，消耗功率皆為16mW。
本篇論文在LNA1中主要的研究項目有二項，第一項：如何讓fold-cascode在低電壓和低功率的操作下，同時達到低雜訊的效果，第二項：如何利用切換式電感切換LNA所操作的頻段；而在LNA2中主要的研究項目在於改善Inter-matching之間的阻抗匹配對於線性度的影響。

Recently years, in the century of speedy development wireless communication, this tendency that the mobile phone have communication and network is more and more important. Developing SOP (System on Package) and SOC (System on chip) is the mainstream. However, the receiver that having GSM and WLAN standards has been height concerned. For this receiver, if using a direct conversion structure, we need the low noise amplifier that operates in different frequency, amplify the signal of GSM and WLAN form antenna respectively. The direct way is to integrate two LNA’s for GSM and WLAN respectively. However, the chip area consumption will be increased and thus the cost increases. For the cost down reason, it becomes important to develop a re-configurable LNA circuit that can provide the frequency either in the GSM (1.8GHz) band or in the WLAN (2.4GHz) band. Moreover, by using fold-cascode structure achieve advantages of low voltage and low power.
In this thesis, we try to develop the LNA1 and the LNA2 that can achieve GSM and WLAN standard at the same time. By way of switching the inductor, the operation of frequency can either in GSM band or in WLAN.
In this research is fabricated in TSMC 0.18μm 1P6M CMOS process. In LNA1 structure, the average forward S21 are 13.347 dB (GSM) and 11.324 dB (WLAN), the reverse isolation S12 is under –40 dB, the S11 are –13 dB(GSM)
and –20 dB (WLAN), the noise figure are 2.9 dB(GSM) and 3.4dB (WLAN), IIP3 are –6 dBm (GSM) and –1 dBm (WLAN) and the circuit power consumption is only 8.23mW. The LNA2 is designed for not to effect operation frequency of LNA1 after designing input matching of Mixer, thus added buffer designing in LNA1. In LNA2 structure, the average forward S21 are 10.893 dB (GSM) and 10.673 dB(WLAN), the reverse isolation S12 is under –60 dB, the S11 are –13 dB(GSM) and –17 dB (WLAN), the noise figure are 3.0 dB (GSM) and 3.2dB (WLAN), IIP3 are –7.2 dBm (GSM) and –5.2 dBm (WLAN) and the circuit power consumption is only 16mW.
The goals of LNA1 are as followed: The first, how to do fold-cascode can operation in low voltage and in low power, moreover, let it achieve low noise at the same time. The second, how to use switch inductor change the operation frequency of LNA. The main research of LNA2 is the relation about the inter-matching of the linearity effect.

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