簡易檢索 / 詳目顯示

回結果列表
研究生： 廖政雄
Liao, Cheng-Hsiung
論文名稱： 具偏移誤差平均化技術的1.8伏特六位元每秒十億次取樣速率快閃式類比數位轉換器
6-bit 1-Gsample/sec Analog-to-Digital Converter with Averaging Techniques
指導教授： 王俊智
Wang, Ching-Chun
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 中文
論文頁數： 84
中文關鍵詞： 類比數位轉換器 、快閃式 、平均
外文關鍵詞： ADC, averaging, flash
相關次數： 點閱：70  下載：2 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 　　本論文提出一個6位元每秒十億次取樣頻率的類比數位轉換器，此轉換器適用於光碟通道讀取技術的需求，採用快閃式架構來實現這個高速的類比數位轉換器。使用全差動的電路結構來提高整個系統的效能。平均化電阻網路可以用來抑制由前置放大器與比較器所造成的偏移電壓，泡沫錯誤與準穩態錯誤的問題，需要做特別的考量與解決，因此，在高速操作時的SNDR才不會降低。
    　　根據模擬結果，此轉換器的最大取樣頻率為1GHz，在輸入頻率為496MHz時的情況下，可得到SNDR為33.1dB。此轉換器採用1.8伏特的電源電壓，在1-Gsample/sec的取樣頻率下，功率消耗為181mW。採用TSMC 0.18μm 1P6M的混合訊號製程來實現，整個晶片的面積為1,06x1.06mm2。

    　In this paper, a 6-bit 1Gsample/sec CMOS analog-to-digital converter is proposed. The application of the 6-bit A/D converter is targeted for using in a disk-drive read channel. A flash structure is adopted to implement the high-speed A/D converter. Using a fully differential architecture enhances the system performance. Averaging resistance networks are utilized to suppress offset voltages from pre-amplifiers and comparators. The issues of bubble error and metastability were considered specially and resolved in the design; therefore, the SNDR at high frequency is not degraded.

    　The simulation result, shows that the maximum sampling speed of the proposed ADC structure can achieve 1GHz. The SNDR at the input frequency of 496MHz is 33.1dB. The power consumption of the converter with 1.8V supply is 181mW at 1-Gsample/sec. The chip area is 1.06x1.06mm2 in TSMC 0.18μm CMOS 1P6M mixed-signal process.

    第一章　緒論..........................................................1 1.1　研究動機.........................................................1 1.2　論文架構....................................................................4 第二章　高速類比數位轉換器架構........................................5 2.1　前言.............................................................5 2.2　快閃式類比數位轉換器（Flash ADC）................................6 2.3　兩階式類比數位轉換器（Two-step ADC）.............................9 2.4　管線式類比數位轉換器（Pipeline ADC）............................13 2.5　摺疊式類比數位轉換器（Folding ADC）.............................16 2.6　時間分離式類比數位轉換器（Time Interleaved ADC）................19 第三章　快閃式類比數位轉換器的實現...................................21 3.1　系統架構........................................................21 3.2　參考電壓源電阻串................................................23 3.3　前置放大器與比較器..............................................26 3.3.1　前置放大器（Preamplifier）....................................28 3.3.2　比較器（Comparator）..........................................30 3.4　偏移電壓平均化技術（Offset Voltage Averaging Technique）........33 3.4.1　平均化的理論..................................................33 3.4.2　平均化技術對INL與DNL的改善....................................35 3.4.3　平均化技術的邊緣效應..........................................37 3.5　泡沫錯誤（bubble error）與準穩態（metastability）...............46 3.5.1　溫度計碼中的泡沫錯誤..........................................46 3.5.2　泡沫錯誤修正（bubble error correction）.......................48 3.5.3　比較器的Metastability錯誤.....................................53 3.5.4　Metastability錯誤的修正.......................................56 3.6　編碼器（Encoder）...............................................58 3.6.1　ROM...........................................................59 3.6.2　Fat Tree編碼器................................................60 3.7　週邊電路........................................................65 3.7.1　TSPCR（True Single Phase Clocked Prgister）...................65 3.7.2　偏壓電路（Bias Circuit）......................................67 3.7.3　時脈產生器（Clock Generator）.................................70 第四章　模擬結果與測試考量...........................................71 4.1　平面配置........................................................71 4.2　佈局考量........................................................72 4.3　模擬結果........................................................75 4.4　測試考量........................................................78 第五章　結論與未來展望...............................................80 5.1　結論............................................................80 5.2　未來展望........................................................81 參考文獻.............................................................82

    [1]　Uyttenhove, K.; Steyaert, M.S.J.;”A 1.8-V 6-bit 1.3-GHz Flash ADC in 0.25-/spl mu/m CMOS”, Solid-State Circuits, IEEE Journal of Volume 38, Issue 7, July 2003
    [2]　Peter Scholtens and Maarten Vertregt,”A 6b 1.6GSample/s Flash ADC in 0.18μmCMOS using Averaging Termination”,IEEE Int. Solid-State CircuitsConf, pp.168-169,F b.2002.
    [3]　M. Choi and A. A. Abidi,“ A 6-b 1.3-Gsample/s A/D Converter in 0.35μm CMOS”, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp.1847-1858, Dec. 2001.
    [4]　K. Nagaraj et al., “A 700-MSample/s 6-b read channel A/D converter with 7-b servo mode,” in IEEE Int. Solid-State Circuits Conf., Feb. 2000, pp. 426–427.
    [5]　Daegyu Lee; Jincheol Yoo; Kyusun Choi; Ghaznavi, J. ,“Fat tree encoder design for ultra-high speed flash A/D converters”, Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on Volume 2, 4-7 Aug. 2002 Page（s）:II-87 - II-90 vol.2
    [6]　Uyttenhove, K.; Marques, A.; Steyaert, M.;”A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction”, Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 200021-24 May 2000 Page（s）:249 - 252
    [7]　David A. Johns and Ken Martin, Analog Integrated Circuit Design. John Wiley & Sons Inc., 1997.
    [8]　Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design. Oxford University Press, Inc., 2002
    [9]　Walt Kester, James Bryant, Sample Data System. Analog Devices Inc.
    [10]　B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
    [11]　Mangelsdorf, C.W.;”A 400-MHz input flash converter with error Correction’’,Solid-State Circuits, IEEE Journal of Volume 25, Issue 1, Feb. 1990 Page（s）:184 – 191.
    [12]　Mehr, I.; Dalton, D.;“A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications”,Solid-State Circuits, IEEE Journal of Volume 34, Issue 7, July 1999 Page（s）:912 - 920
    [13]　Venes, A.G.W.; van-de-Plassche, R.J.;”An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing”,Solid-State Circuits, IEEE Journal of Volume 31, Issue 12, Dec. 1996 Page（s）:1846 - 1853
    [14]　Kanan, R.; Kaess, F.; Declercq, M.;”A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder”,Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume 2, 30 May-2 June 1999 Page（s）:420 - 423 vol.2
    [15]　Matsuzawa, A.; Nalkashima, S.; Hidaka, I.; Sawada, S.; Kodaka, H.; “Shimada, S.;A 6b 1GHz Dual-parallel A/D Converter”,Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International13-15 Feb. 1991 Page（s）:174 – 311
    [16]　K.-L. Lin, Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems, doctoral thesis at Gerhard-Mercator-University of Duisburg, Duisburg, Germany, 2002.
    [17]　Yao, L.; Steyaert, M.; Sansen, W.;”A 1.8-V 6-bit flash ADC with rail-to-rail input range in 0.18μm CMOS”,ASIC, 2003. Proceedings. 5th International Conference on Volume 1, 21-24 Oct. 2003 Page（s）:677 - 680 Vol.1
    [18]　Vandenbussche, J.; Uyttenhove, K.; Lauwers, E.; Steyaert, M.; Gielen, G.;”Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter”,Design Automation Conference, 2002. Proceedings. 39th 10-14 June 2002 Page（s）:449 - 454
    [19]　Jincheol Yoo; Kyusun Choi; Tangel, A.;”A 1-GSPS CMOS flash A/D converter for system-on-chip applications” VLSI, 2001. Proceedings. IEEE Computer Society Workshop on 19-20 April 2001 Page（s）:135 - 139
    [20]　Qiuting Huang; Rogenmoser, R.;”Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks”,Solid-State Circuits, IEEE Journal of Volume 31, Issue 3, March 1996 Page（s）:456 – 465

    下載圖示 校內：2010-08-31公開
    校外：2015-08-31公開
    QR CODE