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研究生：	楊忠明 Yang, Chung-Ming
論文名稱：	具單相位時脈及電容平均之8-bit 500MS/s快閃式類比數位轉換器 An 8-bit 500MS/s Flash ADC with Capacitor Averaging and a Single-Phase Clock
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	86
中文關鍵詞：	單相位、電容平均、快閃式、類比數位轉換器
外文關鍵詞：	Single-phase, Capacitor averaging, flash, ADC
相關次數：	點閱：78 下載：0
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本論文中實現一個八位元每秒五億次取樣快閃式類比數位轉換器，並提出一個具有單相位時脈的電容平均化技術。電阻網路平均化技術可以有效的消減快閃式類比數位轉換器中比較器間的隨機偏移誤差值，但在電阻網路的邊界會產生非對稱的問題必須靠額外的電路解決，因此會造成更大的功率消耗以及信號範圍，自動歸零機制是另一有效抑制隨機偏移誤差的方法，但在連續信號轉換的應用上，要將一無空轉時間的自動歸零機制實現於一高速低潛伏的快閃式類比數位轉換器是相當困難的。本論文提出的電容平均化技術沒有邊界效應的限制，具有消減偏移誤差值的作用並因此縮小了第一級前置放大器的面積。又此技術是以自動歸零機制為主幹，故提出了一個開關式前置放大器來避免傳統自動歸零機制必須使用非重疊時脈相位的限制與消除高速自動歸零機制對輸入端的干擾。此外，相對於近年來所發表的自動歸零機制快閃式類比數位轉換器所需多相位時脈，所提出的技術具有單一相位控制的優點並避免了同步的問題。內插技術亦使用於此設計中，用來降低輸入負載前置放大器數目以及差值非線性誤差。
此快閃式類比數位轉換器之實現是採用TSMC 0.18微米，1P6M互補型金氧半混合信號製程，面積為1.18微米平方。量測結果顯示此設計在500MHz的操作速度下，輸入訊號小於200MHz時，有大於40dB的SNDR動態表現

In this thesis, an 8-bit 500MS/s Flash ADC is implemented, and a capacitor averaging with single-phase technique is proposed. Averaging networks suppress the random offset efficiently between the comparators in flash ADCs, but it causes limitations at the averaging network boundaries. Although the effect can be resolved by additional terminal circuits, it costs larger power consumption and input headroom. Auto-zeroing technique is another effective way to reduce the error, but it is difficult to implement auto-zeroing without idle time in a high speed low latency flash for continuous data conversion. This thesis proposed Capacitor averaging technique without boundary limitation can alleviate random offset, and thus, reduce the area of first preamplifier stage. Since the technique is based on auto-zeroing technique, a switching preamplifier is provided to avoid non-overlap control signals requirement by conventional auto-zeroing ADCs and eliminate the interference caused by the high speed auto-zeroing operation at input nodes. Besides, the proposed technique has the merit of a single clock phase control to avoid synchronous issues since multi-clock phase are necessary for recent published flash ADCs with auto-zeroing technique. Interpolation technique is also used in this design to reduce input loading, preamplifier number and differential nonlinearity (DNL) error in the ADC.
The flash ADC is fabricated in TSMC 0.18m 1P6M CMOS technology and occupies an area of 1.18mm2. The measurement results show that this design can achieve an operating rate of 500MHz with SNDR>40dB when input frequency < 200MHz.

Introduction.....................	1
1	Motivation...........................	1
2	Organization.............................	3
Error Analysis of Flash ADC.............	4
1	Quantization Error..........................	4
2	Noise..............................	7
3	Offset Mismatch..........................	9
4	Clock Skew Effect..........................	13
5	Signal Dependent Comparator Delay Error................	16
6	Kickback ...................................	20
7	Metastability and Hysteresis........................	21
8	Bubble Error.....................	23
Proposed Technique of the Flash ADC.............	 25
1	Interpolation Technique.....................	25
1.1	Interpolation Type..........................	27
1.2	Interpolation Analysis.........................	29
2	Auto-zeroing Technique........................	31
2.1	Auto-zeroing Principle...................	31
2.2	Auto-zeroing Topology....................	32
2.3	Modified Auto-zeroing..................	34
3	Averaging Technique.......................	37
3.1	Resister Averaging Network...............	38
3.2	Offset Reduction with Averaging Network..........	40
3.3	Mathematic Derivation of Averaging Network..........	42
4	Reinterpolation Technique....................	45
5	Calibration Technique.........................................	47
6	Proposed Capacitor Averaging with Single-Phase Clock.........	48
Circuit Design of the Flash ADC.............	54
1	The Architecture of Proposed ADC....................	54
2	Reference Ladder Consideration...................	56
2.1	Effect to the Accuracy of Resistor Ladder...........	56
2.2	Matching Behavior of the Resistor Ladder...........	56
2.3	Input Feed-through of the Resistor Ladder...................	57
3	Front-End Track and Hold Circuit.................	59
4	Anti-kickback Network.........................................	61
5	Comparator Circuit Design....................	61
5.1	Circuit Topology and Consideration............	62
5.2	Switching Preamplifier..................	63
5.3	Second Stage Amplifier................................	64
5.4	Latch Circuit..........................................	65
5.5	DFF................................................	67
6	Implementation of Digital Encoder...............	68
7	Timing Generator Circuit......................	68
8	Floor Plan and Layout.....................	72
Measurement Results................. 	74
1	Power Supply Partition...................... 	74
2	Measurement Setup..................... 	75
3	PCB Design Consideration.................... 	76
3.1	Transmission Line Effect.................	76
3.2	Crosstalk.........................	76
3.3	Decoupling..................... 	76
3.4	PCB Fabrication...................... 	77
4	Experimental Results....................... 	78
Conclusion and Future Work..............	81
Reference...............................	83
                                    

[1] G. Gielen and E. Paulus, “An 8b 600 MS/s 200mW CMOS folding A/D converter using an amplifier preset technique,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 254–255.
[2] X. Jiang, Z. Wang, and M. F. Chang, “A 2 GS/s 6b ADC in 0.18um CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 322–323.
[3] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-um CMOS,” in IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847–1858, Dec. 2001.
[4] Y. Yoshii, K. Asano, M. Nakamura, and C. Yamada, “An 8 bit, 100 MS/s flash ADC,” in IEEE J. Solid-State Circuits, vol. SSC-19, pp. 842–846, Dec. 1984.
[5] B. Nauta and A. G.W. Venes, “An 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter,” in IEEE J. Solid-State Circuits, vol. 30, pp. 1302–1308,
Dec. 1995.
[6] [11] C. S. G. Conroy, D. W. Cline, and P. R. Gray, “An 8-b 85-MS/s parallel pipeline A/D converter in 1-um CMOS,” in IEEE J. Solid-State Circuits, vol. 28, pp. 447–454, Apr. 1993.
[7] B. Razavi and B. A. Wooley, “Design techniques for high-speed, high resolution comparators,” in IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec, 1992.
[8] K. Kattmann and J. Barrow, “A technique for reducing differential nonlinearity errors in flash A/D converters,” in Proc. IEEE Int. Solid State Circuits Conf., pp. 170-171, 1991.
[9] H. Kimura, A. Matuszawa, T. Nakamura, and S. Sawada, “A 10-b 300-MHz interpolated-parallel A/D converter,” in IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 438-446, Apr. 1993.
[10] Chun-Wei Hsu and Tai-Haur Kuo, “6-bit 500MHz Flash A/D Converter with New Design Techniques,” IEE Proceedings-Circuits, Devices and Systems, Vol. 150, No 5, pp. 460-464, Oct. 2003. (SCI, EI)
[11] Uyttenhove K, Steyaert MSJ, “Speed-power-accuracy tradeoff in high-speed CMOS ADCs,” in IEEE Transactions on Circuits And Systems II-Analog And Digital Signal Processing, vol. 49, no. 4, pp. 280-287, Apr. 2002.
[12] William T. Colleran, “A 10-bit, 100MS/s A/D Converter using Folding, Interpolation,
and Analog Encoding,” Ph.D. dissertation, UCLA, Dec. 1993.
[13] Claude-Alain Gobet and Alexander Knob, “Noise Analysis of Switched Capacitor Networks,” in IEEE Transaction on Circuits and Systems, vol. 30, no. 1, pp. 37-43, Jan. 1983.
[14] Chun-Wei Hsu, “A 6-Bit Flash A/D Converter With New Dwsign Techniques,” Master thesis, NCKU, 2002.
[15] Michael Byung Choi, “A 6-bit 1.3GSample/s A/D Converter in 0.35um CMOS,” Ph.D. dissertation, UCLA, 2002.
[16] M. J. M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching preperties of MOS transistor,” in IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1439, Oct. 1989.
[17] Ardie G. W. Venes and Rudy J. van de Plassche, “An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” in IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1846–1853, Dec. 1996.
[18] Selim Saad Awad, “Analysis of Accumulated Timing-Jitter in the time Domain,” in IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 69–73, Feb. 1998.
[19] CMOS Integerated Analog-to-Digital and Digital-toAnalog Converters.
[20] Hiroshi Kimura, Akira Matsuzawa, Takashi Nakamura and Shigeki Sawada, “A 10-b 300-MHz Interpolated-Parallel A/D Converter, ” in IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 1846–1853, Apr. 1993.
[21] Michael P. Flynn and David J. Allstot, “CMOS Folding A/D Converters with Current-Mode Interpolation,” in IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1248–1257, Sep. 1996.
[22] J. Doernberg, P. R Gray and D. A. Hodges, “A 10-Bit 5-Msample/s CMOS Two-Step Flash ADC,” in IEEE J. Solid-State Circuits, vol. SC-24, no. 9, pp. 241–249, Apr. 1998.
[23] Xicheng Jiang and Mau-Chung Frank Chang, “A 1-GHz Signal Bandwidth 6-bit CMOS ADC With Power-Efficient Averaging,” in IEEE J. Solid-State Circuits, vol.40, no. 2, brief, Feb. 2005.
[24] K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm” in IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1887–1895, Dec. 1997.
[25] P. Scholtens and M. Vertregt, “A 6-b 1.6-Gsamples/s flash ADC in 0.18-um CMOS using averaging termination,” in IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1599–1609, Dec. 2002.
[26] Y. T. Wang and B. Razavi, “An 8-Bit, 150-MS/s CMOS A/D Converter,” in IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 308–317, Mar. 2000.
[27] R. Taft, C. Menkus, M. R. Tursi, O. Hidri, and V. Pons, “A 1.8 V 1.6 GS/s 8b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 252–253.
[28] C. Huang and J.Wu, “A background comparator calibration technique for flash analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 52, pp. 1732–1740, Sep. 2005.
[29] Zhengyu Wang and Mau-Chung Frank Chang,” A 600-MSPS 8-bit CMOS ADC Using Distributed Track-and-Hold with Complementary Resistor Capacitor Averaging” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, Dec. 2008.
[30] R. J. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters ,
Kluwer Academic Publisher, 1994.
[31] B. Razavi, “Design of Dample-and-Hold Amplifiers for High-Speed Low-Voltage A/D Converters” in IEEE Custom Integrated Circuits Cond., pp. 5.1.1-5.1.4, 1997.
[32] R. Taft, C. Menkus, M. R. Tursi, O. Hidri, andV. Pons, “A 1.8V 1.6 GS/s8b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 47, Feb. 2004, pp. 252–253.
[33] M. J. M Pelgrom, A. C. J. Diumaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” in IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1440, Oct. 1989.
[34] Koen Uyttenhove et al., “Design techniques and Implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D Converter,” in IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 483–494, Mar. 2003.
[35] G. M. Yin, F. Op't Eynde, and W. Sansen, “A High-Speed CMOS Comparator with 8-b Resolution,” in IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208–211, Feb. 1992.
[36] G. Gielen, H.Walscharts, andW. Sansen, “ISAAC: a symbolic simulator for analog integrated circuits,” in IEEE J. Solid-State Circuits, vol. 24, pp. 1587–1597, Dec. 1989.
[37] G. Van der Plas, W. Daems, E. Lauwers, J. Vandenbussche, W. Verhaegen, G. Gielen, and W. Sansen, “Symbolic analysis of CMOS regenerative comparators,” in Proc. Eur. Conf. Circuit Theory and Design, Aug. 1999, pp. 86–89.
[38] Robert C. Taft, Senior, Chirs A. Menkus, Maria Rosaria Tursi, Ols Hidri, Valerie Pons, “A 1.8v 1.6-GSample/s 8-b Self-Calibrating Folding ADC With 7.26 ENOB AT Nyquist Frequency,” IEEE J. Solid-State Circuits, vol. 39, no. 12, Dec. 2004.
[39] Ivan Bogue and Michael P. Flynn, “A 57dB SFDR Digitally Calibrated 500MHz Folding ADC in 0.18um digital CMOS” IEEE Custom Intergrated Circuits Conference, 2007.
[40] Robert C. Taft, Pier Andrea Francese, Maria Rosaria Tursi, Alan MacKenzie, Tobias Höhn, Philipp Schmitz, Heinz Werker, Andrew Glenny, “A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency” IEEE J. Solid-State Circuits, vol. 44, no. 12, Dec. 2009.

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