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研究生： 蘇家緯
Su, Chia-Wei
論文名稱： 用於演算法階層之功率管理導向的硬體分割法
Power-Management Aware Hardware Partitioning Methods at Algorithmic Level
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 60
中文關鍵詞： 分割演算法 、功率管理
外文關鍵詞： power management, partitioning algorithm
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    • 在數位電路系統，利用功率管理機制所能節省的能量消耗取決於休眠時間的長短。以往功率管理機制在暫存器轉移階層以下階層實現。然而，調整設計的彈性將受限於實現的階層。我們提出在較早的設計階段規劃功率管理機制的概念。因此，可節省的能量消耗將可增加。我們提出的方法從演算法階層開始進行功率管理導向的硬體分割演算法。使用了基因演算法及反覆改進啟發式演算法來探索適合功率管理的硬體分割。實驗結果顯示使用提出的演算法所得到的結果與利用窮盡式演算法相近。

    In digital systems, the amount of energy can be saved by power management depending on the length available idle time. Transitionally power management is considered and implemented at register-transfer level. However, the level of flexibility for changing the design is limited. We propose to move the power-management planning to an earlier design stage. Thus, the energy saving can be maximized. The proposed approach starts from algorithmic level to perform power-management oriented hardware partitioning. The hybrid genetic and iterative heuristic can explore for near-to-optimal cases under practical conditions. Experimental results show that our fast exploration is very close to the exhaustive approach.

    Chapter 1 Introduction 1 1.1 Sources of power consumption 2 1.2 Dynamic power management 3 1.3 Partitioning of VLSI circuits and systems 7 1.3.1 Iterative improvement 8 1.3.2 Simulated annealing 9 1.3.3 Tabu search 10 1.3.4 Genetic algorithm 10 1.4 Motivation 11 1.5 Contributions 13 1.6 Thesis organization 13 Chapter 2 Literature Survey 14 2.1 Power-management aware methodology in high-level synthesis 14 2.2 Power-management aware partitioning 16 Chapter 3 Proposed Algorithm 20 3.1 Preliminary 20 3.2 Procedures 21 3.3 Parsing and extraction stage 22 3.4 Scheduling stage 25 3.5 Assignment stage 29 3.6 Partitioning stage 30 3.6.1 Problem definitions 31 3.6.2 Genetic algorithm 34 3.6.3 Iterative improvement algorithm 38 Chapter 4 Experimental Results 40 4.1 Test cases 40 4.2 Power and timing model 40 4.3 Evaluative function 41 4.4 Experimental results and discussion 44 4.5 Verification 52 Chapter 5 Conclusions and Future Works 55 5.1 Conclusions 55 5.2 Future works 56 References 57

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