傳統量測時脈抖動的技術要量測到微秒(picosecond)的精確度需要非常昂貴的測試儀器。本篇論文提出了一種應用於鎖相迴路(Phase-Locked Loops)之低成本的時脈抖動量測技術。這提出的方法主要針對鎖相迴路對電源雜訊非常靈敏而且時脈抖動產生的主因來自於電源雜訊。在這提出的技術可以讓我們利用較低成本的測試儀器去量測時脈抖動。

　　本篇論文研究的方向就是去發展一套有效分析時脈抖動的方法。我們直接在所定義的“時脈抖動時域”下去處理時脈抖動，進而取代傳統處理時脈抖動所用的“相位時域”。當在電路層次(Circuit-Level)模擬時運用這個方法可以讓我們非常容易的去觀察並且分析時脈抖動的行為。最後一個運用“時脈抖動時域”原理所發展而成的內建式之鎖相迴路的時脈抖動量測電路被提出來而且驗證。

　　Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost test instrumentation. In this thesis, we present a low-cost technique for jitter measurement of phase-locked loops (PLLs). The proposed approach exploits the high sensitivity of PLL’s jitter to power supply variations, and is applicable to PLLs whose jitter is predominantly due to power supply noise. The technique enables the potential of using of a medium-accuracy tester for the production test of PLL’s jitter.

　　The aim of this thesis is to develop an efficient methodology for analyzing jitter. Instead of describing the jitter in the traditional phase domain, we deal with the jitter directly in the defined “jitter domain”. In this manner, it becomes much more easier to observe and then analyze the behavior of jitter at the circuit-level simulation. After that a simple on-chip PLL’s jitter measurement circuit, which utilizes the jitter-domain principle, is proposed and demonstrated.

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