在本論文中，我們分別探討了零點三五微米製程高壓N型橫向擴散與P型汲極延伸金氧半電晶體之熱載子導致的元件退化行為與機制。
當N型橫向擴散電晶體應用在切換電路中而且負載為電感性負載時，在導通狀態與靜止狀態切換的瞬間，電晶體將會被強迫發生靜止態累增崩潰，此時元件將受到汲極端與閘極邊緣處的高電場作用產生大量撞擊游離化而導致元件特性上的退化：導通電阻的增加。造成元件退化的主要機制為崩潰引起的電洞注入所產生的矽與氧化層接面的介面能態(interface states)以及氧化層內的缺陷正電荷(positive oxide-trapped charges)，其中介面能態會使得電阻增加而缺陷正電荷會導致電阻下降，元件退化的行為也會因為介面能態及缺陷正電荷生成速率的飽和而趨緩。除此之外我們發現提高汲極漂移區的參雜濃度能有效降低累增崩潰時介面態的生成而改善導通電阻的退化。
除了導通電阻的增加，靜止態崩潰也會造成元件崩潰電壓的提高，我們推測崩潰電壓的增加是由於電洞注入所產生的氧化層缺陷正電荷。電性模擬的結果顯示缺陷正電荷會吸引更多的電子到氧化層表面而改變了汲極端閘極邊緣下的電力線分布，同時降低了垂直方向電場及撞擊游離化的速率而增加崩潰的電壓。
當N型橫向擴散金氧半電晶體操作在一般導通狀態下，高操作電壓所引起的熱載子效應亦為元件退化的一個重要來源，熱載子所引起的介面能態分布將會受到閘極偏壓的影響而改變。產生在閘極下的累積區(accumulation region)裡的介面能態對汲極電流的影響很小，相對地，假使通道內(channel region)表面沒有介面能態的產生，那產生在汲極端閘極側壁下(spacer region)的介面能態將會導致汲極線性區電流明顯的退化。實驗顯示增加汲極漂移區的參雜濃度可以降低汲極線性區電流的退化。由電性模擬發現增加汲極漂移區的參雜濃度雖然使累積區內的撞擊游離化速率上升，但同時降低了側壁下的撞擊游離速率，因此改善了汲極線性區電流退化的程度。
最後，我們將探討P型汲極延伸金氧半電晶體在熱載子測試下的汲極電流變化。由於受到電子注入產生電子缺陷的影響，被捕捉到的電子增加了P型漂移區(drift region)的表面濃度，汲極飽和區及線性區電流在熱載子測試之後都會有增加的現象，除此之外我們發現電流增加的程度與累積區的大小有關，累積區越大的元件在熱載子測試後產生較小的電流變化。電性模擬顯示在飽和區與線性區偏壓條件下的電流路徑對累積區長度與電流改變量有重大的影響。

In this dissertation, the hot-carrier-induced degradation in 0.35 μm n-type self-aligned lateral double-diffused MOSFET (LDMOS) and p-type drain-extended MOSFET (DEMOS) devices are studied.
When the nLDMOS device is used in a power switching circuits with an unclamped inductive load, the off-state avalanche breakdown occurs during on-state to off-state transient. The device degrades because of the high electric field and impact ionization located near the drain side poly-gate edge. The main mechanism of device degradation is the interface states and positive oxide-trapped charges created by breakdown-induced hole injection. The interface states degrade device turn-on resistance (Ron) however
positive oxide-trapped charges reduce the series resistance. The degradation has the tendency to saturate, which in consistent with the saturation of interface states and oxide-trapped charges generation. Moreover, increasing the device drift drain (NDD) region dosage can reduce the generation of interface states, leading to an improved degradation.
Besides Ron degradation, the off-state breakdown voltage (BVdss) increases while off-state avalanche breakdown occurs. It is suggested that the main mechanism of BVdss increase is the hole trapping created by hole injection. TCAD simulation reveals that hole trapping attract mirror electrons at Si/SiO2 surface and lower the potential contour crowding and reduce lateral and vertical electric field under drain side spacer. As a consequence, the impact ionization rate at breakdown point is lowered, leading to a higher breakdown voltage.
While the nLDMOS devices operate on on-state, the devices degrade due to high operating voltage and high electric field. The location of hot-carrier-induced interface states varies with different stress gate voltage. The interface states located in accumulation region under poly-gate have little effect on Idlin degradation. As a result, interface states located in drain-side spacer region dominate Idlin degradation when interface states located in channel region are negligible. In our experiment, increasing
NDD dosage results in improved Idlin degradation. TCAD simulations reveal that high NDD dosage increases impact ionization rate in accumulation and channel regions, but reduces impact ionization rate in spacer region, leading to an improved Idlin degradation.
Finally, the drain current shifts after hot carrier stress in pDEMOS transistors is studied. The drain saturation (Idsat) and linear current (Idlin) both increase after hot carrier stress due to hot electron injection and electron trapping. Electron trapping reduces the resistance of p-drift region hence increases drain current. Moreover, the current shifts are dependent on the length of drain extended region under poly gate. Device with longer drain extended under poly produces less current increment after Igmax stressing. TCAD simulation reveals that the path of current flow under Idlin and Idsat condition can explain the relation between the drain extended overlap and the current shifts.

Chapter 1
[1] P. L. Hower and S. Pendharkar, “Short and long-term safe operating area considerations in LDMOS transistors,” in Proc. Int. Reli. Phys. Symp., pp. 545-550, 2005.
[2] H. J. Sigg, G. D. Vendelin, T. P. Cauge, and J. Kocsis, “D-MOS transistor for microwave applications,” IEEE Trans. Electron Devices, vol. 19, no. 1, pp. 45-53, 1972.
[3] C. Contiero, P. Galbiati, M. Palmieri, and L. Vecchi, “LDMOS Implementation by Large Tilt Implant in 0.6 m BCD5 Process, Flash Memory Compatible,” in Proc. Symp. Power Semicond. Devices and ICs, pp. 75-78, 1996.
[4] J. Apels, H. Vaes and J. Verhoeven, “High voltage thin layer devices (RESURF DEVICES),” in IEDM Tech. Dig., pp. 238-241, 1979.
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[6] D. G. Lin, S. L. Tu, Y. C. See, and P. Tam, “A Novel LDMOS Structure With A Step Gate Oxide,” in IEDM Tech. Dig., pp. 963-966, 1995.
Chapter 2
[1] P. Heremans, J. Witters, G. Groeseneken, and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, no. 7, pp. 1318-1335, 1989.
[2] J. F. Chen, K. M. Wu, J. R. Lee, Y. K. Su, H. C. Wang, Y. C. Lin and S. L. Hsu, “Characteristics and Improvement of Hot-Carrier Reliability in Sub-Micrometer High-Voltage Double Diffused Drain Metal-Oxide-Semiconductor Field-Effect Transistors”, Jpn. J. Appl. Phys., vol. 46, no. 4B, pp. 2019-2022, 2007.
Chapter 3
[1] S. Pendharkar, T. Efland, and C. Y. Tsai, “Analysis of high current breakdown and UIS behavior of Resurf LDMOS (RLDMOS) devices,” in Proc. Symp. Power Semicond. Devices and ICs, pp. 419-422, 1998.
[2] K. Fischer and K. Shenai, “Dynamics of power MOSFET switching under unclamped inductive loading conditions,” IEEE Trans. Electron Devices, vol. 43, no. 6, pp. 1007-1015, Jun. 1996.
[3] S. Manzini and C. Contiero, “Hot-electron-induced degradation in high-voltage submicron DMOS transistors,” in Proc. Int. Reli. Phys. Symp., pp. 65-69, 1996.
[4] R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, “Hot-carrier reliability in submicrometer LDMOS transistors,” in IEDM Tech. Dig., pp. 371-374, 1997.
[5] D. Brisbin, A. Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications,” in Proc. Int. Reli. Phys. Symp., pp. 105-110, 2002.
[6] P. Moens, G. Van den bosch, C. De Keukeleire, R. Degraeve, M. Tack, and G. Groeseneken, “Hot hole degradation effects in laternal nDMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1704-1710, Oct. 2004.
[7] J. F. Chen, K. M. Wu, K. W. Lin, Y. K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” in Proc. Int. Reli. Phys. Symp., pp. 560-564, 2005.
[8] C. C. Cheng, K. C. Tu, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Investigation of hot carrier degradation modes in LDMOS by using a novel three-region charge pumping technique,” in Proc. Int. Reli. Phys. Symp., pp. 334-337, 2006.
[9] D.Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, S. Krishnan, and M. A. Alam, “Universality of off-state degradation in drain extended NMOS transistors,” in IEDM Tech. Dig., pp. 751-754, 2006.
[10] J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, C. M. Liu, and S. L. Hsu, “Off-State Avalanche-Breakdown-Induced On-Resistance Degradation in Lateral DMOS Transistors,” IEEE Electron Devices Lett., vol. 28, no. 11, pp. 1033-1035, Nov. 2007.
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[14] A. Melik-Martirosian and T. P. Ma, “Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices,” in IEDM Tech. Dig., pp. 93-96, 1999.
[15] C. Chen and T. P. Ma, “Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, no. 2, pp. 512-520, Feb. 1998.
[16] P. Heremans, J. Witters, G. Groeseneken, and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, no. 7, pp. 1318-1335, Jul. 1989.
[17] D. S. Ang and C. H. Ling “A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 149-159, Jan. 1998.
[18] K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu, and J. R. Shih, “Anomalous reduction of hot-carrier-induced on-resistance degradation in n-type DEMOS transistors,” IEEE Trans. Device and Materials Reliability, vol. 6, no. 3, pp. 371-376, Sep. 2006.
Chapter 4
[1] P. Moens, J. Mertens, F. Bauwens, P. Joris, W. De Ceuninck, and M. Tack, “A comprehensive model for hot carrier degradation in LDMOS transistors,” in Proc. Int. Reli. Phys. Symp., pp. 492-497, 2007.
[2] J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, C. M. Liu, and S. L. Hsu, “Off-State Avalanche-Breakdown-Induced On-Resistance Degradation in Lateral DMOS Transistors,” IEEE Electron Devices Lett., vol. 28, no. 11, pp. 1033-1035, Nov. 2007.
[3] P. Moens, G. Van den bosch, D. Wojciechowski, F. Bauwens, H. De Vleeschouwer, and F. De Pestel, “Charge Trapping Effects and Interface State Generation in a 40 V Lateral Resurf pDMOS Transistor,” in Proc. ESSDERC Symp., pp. 407-410, 2005.
[4] D. Brisbin, A. Strachan, P. Chaparala, “PMOS Drain Breakdown Voltage Walk-in: A New Failure Mode in High Power BiCMOS Applications,” in Proc. Int. Reli. Phys. Symp., pp. 265-268, 2004.
[5] A. Raychaudhuri, M. J. Deen, W. S. Kwan, and M. I. H. King, “Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFET’s,” IEEE Trans. Electron Devices, vol. 43, no. 7, pp. 1114-1122, 1996.
Chapter 5
[1] P. L. Hower and S. Pendharkar, “Short and long-term safe operating area considerations in LDMOS transistors,” in Proc. Int. Reli. Phys. Symp., pp. 545-550, 2005.
[2] V. O’Donovan, S. Whiston, A. Deignan, and C. N. Chleirigh, “Hot carrier reliability of lateral DMOS transistors,” in Proc. Int. Reli. Phys. Symp., pp. 174-179, 2000.
[3] D. Brisbin, A. Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications,” in Proc. Int. Reli. Phys. Symp., pp. 105-110, 2002.
[4] P. Moens, G. V. den bosch, and G. Groeseneken, “Hot-carrier degradation phenomena in lateral and vertical DMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 623-628, 2004.
[5] J. F. Chen, K. M. Wu, K. W. Lin, Y. K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” in Proc. Int. Reli. Phys. Symp., pp. 560-564, 2005.
[6] C. C. Cheng, K. C. Du, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Investigation of Hot Carrier Degradation Modes in LDMOS by using a Novel Three-Region Charge Pumping Technique,” in Proc. Int. Reli. Phys. Symp., pp. 334-337, 2006.
[7] A. Shibib, S. Xu, Z. Xie, P. Gammel, M. Mastrapasqua, and I. Kizilyalli, “Control of hot carrier degradation in LDMOS devices by a dummy gate field plate: experimental demonstration,” in Proc. Symp. Power Semicond. Devices and ICs, pp. 233-235, 2004.
[8] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot-hole injection degradation model for lateral nDMOS transistors,” in IEDM Tech. Dig., pp. 877-880, 2001.
[9] P. Moens, G. V. den bosch, C. De Keukeleire, R. Degraeve, M. Tack, and G. Groeseneken, “Hot hole degradation effects in lateral nDMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1704-1710, 2004.
[10] R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, “Hot-carrier reliability in submicrometer LDMOS transistors,” in IEDM Tech. Dig., pp. 371-374, 1997.
[11] C. C. Cheng, J. F. Lin, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Physics and characterization of various hot-carrier degradation modes in LDMOS by using a three-region charge-pumping technique,” IEEE Trans. Device and Materials Reliability, vol. 6, no. 3, pp. 358-363, 2006.
[12] H. J. Sigg, G. D. Vendelin, T. P. Cauge, and J. Kocsis, “D-MOS transistor for microwave applications,” IEEE Trans. Electron Devices, vol. 19, no. 1, pp. 45-53, 1972.
[13] S. C. Sun and James D. Plummer, “Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power Transistors,” IEEE Trans. Electron Devices, vol. 27, no. 2, pp. 356-367, 1980.
[14] P. Heremans, J. Witters, G. Groeseneken, and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, no. 7, pp. 1318-1335, 1989.
[15] A.W. Ludikhuize, “Kirk effect limitations in high voltage IC's,” in Proc. Symp. Power Semicond. Devices and ICs, pp. 249-252, 1994.
[16] J. E. Chung, P. K. Ko, and C. Hu, “A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1362-137, 1991.
[17] S. C. Sun and James D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. 27, no. 8, pp. 1497-1508, 1980.
[18] C. Chen and T. P. Ma, “Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, no. 2, pp. 512-520, 1998.
[19] P. Moens, J. Mertens, F. Bauwens, P. Joris, W. De Ceuninck, and M. Tack, “A comprehensive model for hot carrier degradation in LDMOS transistors,” in Proc. Int. Reli. Phys. Symp., pp. 492-497, 2007.
[20] X. M. Li and M. J. Deen “Determination of interface state density in MOSFETs using the spatial profiling charge pumping technique,” Solid-State Electronics, vol. 35, no. 8, pp. 1059-1063, 1992.
[21] A. Melik-Martirosian and T. P. Ma “Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices,” in IEDM Tech. Dig., pp. 93-96, 1999.
[22] A. Raychaudhuri, M. J. Deen, W. S. Kwan, and M. I. H. King, “Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFET’s,” IEEE Trans. Electron Devices, vol. 43, no. 7, pp. 1114-1122, 1996.
[23] S. Ogawa and N. Shiono, “Interface-trap generation induced by hot-hole injection at the Si-SiO2 interface,” Appl. Phy. Lett., vol. 61, no. 7, pp. 807-809, 1992.
[24] K. H. Ng, B. B. Jie, Y. D. He, W. K. Chim, M. F. Li, and K. F. Lo, “A comparison of interface trap generation by Fowler-Nordheim electron injection and hot-hole injection using the DCIV method,” in Proc. of Int. Symp. on Physical and Failure Analysis of ICs, pp. 140-144, 1999.
[25] K. M. Wu, Jone F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu, and J. R. Shih, “Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors,” IEEE Trans. Device and Materials Reliability, vol. 6, no. 3, pp. 371-376, 2006.
Chapter 6
[1] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot-hole injection degradation model for lateral nDMOS transistors,” in IEDM Tech. Dig., pp. 877-880, 2001.
[2] P. Moens, G. V. D. Bosch, G. Groeseneken, and D. Bolognesi, “A Unified Hot Carrier Degradation Model for Integrated Lateral and Vertical nDMOS Transistors,” in Proc. Symp. Power Semicond. Devices and ICs, pp. 88-91, 2003.
[3] A.W. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, “Analysis of hot-carrier-induced degradation and snapback in submicron 50V lateral MOS transistors,” in Proc. Symp. Power Semicond. Devices and ICs, pp. 53-56, 1997.
[4] R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, “Hot-carrier reliability in submicrometer LDMOS transistors,” in IEDM Tech. Dig., pp. 371-374, 1997.
[5] K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu, and J. R. Shih, “Anomalous reduction of hot-carrier-induced on-resistance degradation in n-type DEMOS transistors,” IEEE Trans. Device and Materials Reliability, vol. 6, no. 3, pp. 371-376, Sep. 2006.
[6] J. F. Chen, K. M. Wu, J. R. Lee, Y. K. Su, H. C. Wang, Y. C. Lin and S. L. Hsu, “Characteristics and Improvement of Hot-Carrier Reliability in Sub-Micrometer High-Voltage Double Diffused Drain Metal-Oxide-Semiconductor Field-Effect Transistors”, Jpn. J. Appl. Phys., vol. 46, no. 4B, pp. 2019-2022, 2007.
[7] P. Moens, G. Van den bosch, D. Wojciechowski, F. Bauwens, H. De Vleeschouwer, and F. De Pestel, “Charge Trapping Effects and Interface State Generation in a 40 V Lateral Resurf pDMOS Transistor,” in Proc. ESSDERC Symp., pp. 407-410, 2005.
[8] T. C. Ong, P. K. KO, and C. Hu, “Hot-Carrier Current Modeling and Device Degradation in Surface-Channel p-MOSFET's,” IEEE Trans. Electron Devices, vol. 37, no. 7, pp. 1658-1666, 1990.
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