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研究生：	范佐弘 Fan, Tso-Hung
論文名稱：	具有RFCI技術之15位元500KS/s循環式類比數位轉換器 A 15-bit 500KS/s Cyclic A/D Converter with Random Feedback-Capacitor Interchanging Technique
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	86
中文關鍵詞：	類比數位轉換器
外文關鍵詞：	Analog-to-Digital Converter
相關次數：	點閱：55 下載：4
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　　在現今信號處理的應用上，隨著可攜式電子產品需求的快速成長，低功率、低成本、高解析的類比數位轉換器於單晶片系統中為一重要的關鍵元件。循環式類比數位轉換器架構適合用於這些應用中，由於其具備可在小面積內完成高解析的能力。然而實際上，電容不匹配往往會限制住類比數位轉換器的精準度。在本篇論文，一種稱為隨機式回授電容交換技術的被運用在轉換器中，藉此來降低因為電容不匹配所造成的非線性失真。隨機式回授電容交換技術只需要一些簡單的控制邏輯即可實現，因此避免了大量的額外電路。這將會降低電路複雜度、面積、及功率消耗。此外，隨機式回授電容交換技術使得電容大小可以被降低到KT/C雜訊的限制。隨著電容負載的降低，放大器的功率消耗也可以跟著下降。因此，隨機式回授電容交換技術適合使用於低功率及小面積的轉換器上來實現高精準度。
　　為了證明隨機式回授電容交換技術的效用，一個內部時脈操作在八百萬赫茲的十五位元、每秒五十萬次取樣循環式類比數位轉換器被實現，並採用TSMC 3.3伏, 0.35微米, 2P4M CMOS製程製作電路。此轉換器所含的面積為0.6mm2消耗功率為21mW。經由量測結果得知，此隨機式回授電容交換技術能夠有效改善類比數位轉換器的線性度。

　　For modern signal processing applications, low power, low cost, and high resolution ADC is one of the key components in system-on-a-chip (SOC) with the expanding demand for portable products. The cyclic ADCs architecture is suitable for these applications, owing to its ability to achieve high resolution within small silicon area. However, the capacitor mismatch in practical limits the accuracy of ADC. In this thesis, a new random feedback-capacitor interchanging (RFCI) technique is used to reduce nonlinearity caused by capacitor mismatch. Only some simple control logics are required to realize the RFCI technique, avoiding the need for a significant amount of additional hardware. This will reduce circuit complexity, die area, and power dissipation. Moreover, the RFCI technique allows the capacitors to be scaled down to the KT/C noise limit. With a reduced capacitive load, opamp power consumption is also reduced. Hence, RFCI technique is suitable for use in low power and small area case to achieve high accuracy.
　　To demonstrate the effectiveness of RFCI technique, a 15-bit 500KS/s cyclic ADC with internal 8MHz clock rate is implemented in TSMC 3.3V, 0.35μm, 2P4M CMOS process. The ADC occupying 0.6mm2 of active die area dissipates 21mW. The measurement results show that RFCI technique being able to improve the linearity of the ADC.

Introduction.........................................................................	1
1	Motivation...................................................................	1
2	Organization.................................................................	2
	
Review of Analog-to-Digital Converter................................................	4
1	Fundamentals of Analog-to-Digital Converter..........................................	4
2	ADC Performance Metrics..............................................................	5
2.1	Signal-to-Noise Ratio (SNR)..................................................	5
2.2	Spurious Free Dynamic Range (SFDR)...........................................   8
2.3	Signal-to-Noise and Distortion Ratio (SNDR)..................................	9
2.4	Nonlinearity.................................................................   9
3	Review of ADC Architectures..........................................................   11
3.1	Flash ADC....................................................................   11
3.2	Two-Step ADC.................................................................   12
3.3	Pipelined ADC................................................................   13
3.4	Cyclic ADC...................................................................   14
4	Key Building Blocks of Cyclic ADC....................................................   15
4.1	Input Sample and Hold Circuit................................................	16
4.2	Multiplying Digital to Analog Converter......................................	18
4.3	Sub-ADC......................................................................	19
4.4	Digital Error Correction.....................................................	20
5	Summary..............................................................................	23
	
System Analysis and Design of Cyclic ADC.............................................	24
1	Effects of Nonidealities.............................................................	24
1.1	Gain Errors..................................................................	25
1.2	DAC Errors...................................................................	28
1.3	Nonlinearity.................................................................	29
1.4	Opamp incomplete Settling Time...............................................	32
1.5	Thermal Noise................................................................	32
2	Accuracy Requirements................................................................	34
2.1	Opamp DC Gain Requirement....................................................	35
2.2	Opamp Bandwidth Requirement..................................................	36
2.3	Capacitor Matching Requirement...............................................	40
	
Circuit Implementation...............................................................	42
1	Architecture Description.............................................................	42
2	Sample-and-Hold Circuit..............................................................	43
2.1	Operational Amplifier Topologies.............................................	45
2.2	Gain-Boosted Folded-Cascode Amplifier........................................	47
2.3	Switch Design................................................................	53
2.4	Simulation Results...........................................................	56
3	Multiplying Digital to Analog Converter..............................................	57
4	Comparator...........................................................................	59
5	Sub-ADC and Control Logic............................................................   61
6	Digital Error Correction.............................................................	62
7	Timing Generator.....................................................................	63
7.1	Linear Feedback Shift Register Circuit.......................................	64
7.2	Non-overlapping Clock Generator..............................................	65
8	Layout and Floor Plan................................................................	66
9	Simulation Results of Cyclic ADC.....................................................	68
10	Summary..............................................................................	71
	
Test Setup and Measurement Results...................................................	72
1	Test Setup...........................................................................	72
1.1	Power Supply and Ground......................................................	73
1.2	Reference voltage generator..................................................	74
2	Measurement Results..................................................................	76
Conclusion and Future Work...........................................................	82
        Reference............................................................................	83
                                    

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