掃描式測試架構為使用標準元件庫積體電路可測試性設計的主流，而當今典型的積體電路可能包含超過百萬邏輯閘，使得測試時間及測試資料量成為系統單晶片測試的兩個主要考量。先進掃描式測試架構使用輸入腳位壓縮與無失真輸出腳位壓縮之技術，可顯著減少掃描鏈長度且不犧牲錯誤涵蓋率，以解決測試時間及測試資料量所增加的測試成本。然而，缺乏一套自動化軟體協助電路設計人員加入可測試性設計，將增加測試開發時間及人為操作錯誤的發生。本篇論文完成一套自動化設計軟體，可在電路中加入測試架構及產生測試向量與驗證環境和提供輸入腳位及輸出腳位壓縮分析，此軟體包含命令列模式及圖形化操作，具有減少測試開發時間及人為操作錯誤、提高生產力及測試品質、降低測試成本等主要特色。

　　The most commonly used DFT technique for cell-based circuits is the scan-based design. However, because a typical ASIC today may contain more than one million logic gates, the test time and test volume have become two major concerns of the system-on-a-chip (SOC) testing. Advanced Scan Architecture (ASA) based on the previously developed input reduction method and a new zero aliasing output reduction method can significantly reduce the length of the necessary scan chain length with no fault coverage sacrificed for reducing the test time and test volume. 　　　　　　　　However, the test development time and the manual error probabilities may increase if there is no design automatic tool to aid the designers to insert the test architecture. In this thesis, a design automatic tool is developed to insert the ASA into the circuits, to provide the test patterns and verification environment for this architecture, and to analyze the input reduction and output reduction. The developed tool includes the command mode and GUI operations. The main advantages of the design automatic tool are slashing the test development time, eliminating the manual mistakes, improving the productivity and test quality, and reducing test cost.

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