未来按比例缩小的Si MOSFET的前景从根本上受到驱动电流饱和的限制. 应结合具有高载流子迁移率和源极注入速度的SiGe MOSFET通道,以规避这种缩放限制, 并允许短通道MOSFET驱动电流的未来发展.因此,突破传统半导体固有的发展局限和摩尔定律的局限,成为寻找下一代半导体材料并研究其相关工艺的根本任务.基于上述困难,本文提出了一种新的制造工艺方法并寻求采用.即,低温高压退火 (HPA) 和顺序层蚀刻 (sALE) 以及该技术的权宜之计已得到彻底研究.
在本研究的第一部分中,6个大气压的高压退火技术(200-450˚C) 作为高 k/金属栅极金属氧化物半导体电容器的金属后退火.为了验证高压退火(HPA)在提高界面陷阱密度,泄漏问题和平带电压偏移方面的能力,将氧化物陷阱电荷,界面态密度和泄漏电流与其他相同结构的电容器进行了退火处理通过微波退火(MWA)进行比较.HPA 表现出低陷阱密度,表明可能去除电荷陷阱并降低漏电流密度.结果表明, 与高功率微波退火相比,HPA工艺可以有效地减少低温下俘获的电荷,并且低温高压退火后漏电流密度的降低对应于电荷陷阱的减少.低温下的HPA作为高k/金属栅极结构的后金属化退火工艺显示出巨大的潜力,因为它具有不希望的效果,例如Al扩散到介电层中.
在本论文的第二部分中, 针对通过改变工艺参数（例如偏置）来制造MOS电容器,以顺序和连续层蚀刻的形式使用具有射频 (RF) 和Ar/Cl混合物的等离子体的效应,使用原子层沉积Al2O3高k栅极电介质和TiN金属栅极的金属氧化物半导体电容器,然后集成顺序层蚀刻 (sALE) 和连续层蚀刻(cALE) 进行比较以进一步蚀刻下来并制造高质量的MOS电容器. 为了进一步研究, 还分析了 C-V, C-V 滞后, EOT, I-V, 跨导 (gm) 等电气特性. 一个重要的结果/结果表明, 顺序层蚀刻是抑制漏电流密度(Jg) 的合适选择, 获得良好的电容,正平带偏移.此外,在MOS电容器上进行连续层蚀刻可以实现更低的氧化物陷阱电荷 (Qot) 和界面态密度 (Dit).
在本论文的第三部分, 通过在500⁰C ~ 600⁰C的低温下应用连续层刻蚀和高压退火,制造了一种改进的电学特性和低损伤的超薄SiGe FinFET. SiGe FinFET可以有效抑制结泄漏, 因此在 VD = -0.1V 时实现了高 ION/IOFF 比 (3.38 × 106 A/µm). sALE 蚀刻的 FinFET 显示出较小的负阈值电压偏移, 在较低鳍片宽度下改进的 DIBL 以及增强的有效迁移率和较低的界面陷阱密度.由于cALE FinFET阈值电压的突然负移和sALE FinFET的改进情况,DIBL受到很大影响.sALE的DIBL为130 mV/V和172 mV/V的cALE,鳍片宽度为40 nm. 根据理解结果,顺序层刻蚀可以各向异性地刻蚀具有较低表面粗糙度的垂直SiGe Fin结构. 此外,对鳍结构进行高压退火,以恢复等离子体连续蚀刻过程中造成的损坏.sALE 蚀刻 FinFET 的最低表面 (RMS) 为0.17 nm, 而 cALE FinFET的最高RMS为0.28 nm. 对于通过连续层蚀刻技术蚀刻的SiGe FinFET,在鳍宽度= 40 nm 和栅极长度= 100 nm 时获得了88 mV/dec 的最低亚阈值摆动. 根据本研究的结果发现, 在制造 FinFET 器件的高功率方法中,与MWA相比, 顺序层蚀刻技术和高压退火比连续层蚀刻更可靠和成功.

The prospect of future scaling in scaled Si MOSFETs is fundamentally limited by drive current saturation. SiGe MOSFET channels with high carrier mobility and source injection velocity should be incorporated to circumvent this scaling limitation and allow future advances in short-channel MOSFET driving current. As a result, the fundamental task of busting beyond the limitations of traditional semiconductors due to its intrinsic development limitations and Moore's Law has become finding the next generation of semiconductor materials and investigating their related processes. Based on the above-mentioned difficulties, in this thesis a novel approach towards a fabrication process has been brought up and sought to be adopted. i.e., high pressure annealing (HPA) at low temperature and sequential layer etching (sALE) and the expedient of this techniques has been thoroughly investigated.
In the first part of this study, high pressure annealing technique at 6 atm over a wide range of temperature (200-450˚C) was introduced as post metal annealing on high-k/metal gate metal-oxide-semiconductor capacitor. To verify the ability of high-pressure annealing (HPA) in improving interface trap density, leakage issue and flat-band voltage shift, oxide trapped charge, interface state density and leakage current were compared with the other MOS)capacitor with same structure was annealed by microwave annealing (MWA) for comparison. HPA demonstrates low trap density, indicating potential removal of charge traps and reduction in leakage current density. The results show that HPA process is effective to minimize the oxide trapped charged at low temperature than by high power microwave annealing and the reduction in leakage current density after high pressure anneal at low temperature corresponds to the reduction in charge traps. HPA at low temperature demonstrates great potential as the post-metallization annealing process for the high-k/metal gate structure due to its undesired effect like Al diffusion into dielectric layer.
In the second part of this thesis, the effect of plasma with a radio frequency (RF) and an Ar/Cl mixture was used in the form of sequential and continuous layer etching in view of fabricating MOS capacitor by varying the process parameter such bias, working pressure, etc. Metal oxide semiconductor capacitors with Al2O3 high-k gate dielectric deposited by atomic layer deposition and with TiN metal gate was used and then sequential layer etching (sALE) and continuous layer etching (cALE) for comparison was integrated to further etch down and fabricate high quality MOS capacitors. For further investigation, electrical characteristics such as C-V, C-V hysteresis, EOT, I-V, transconductance (gm) were also analyzed. An important outcome/results indicate that sequential layer etching is suitable choice in suppressing leakage current density (Jg), obtains good capacitance, positive flat band shift. Moreover, sequential layer etching on MOS capacitor can achieve lower oxide trap charge (Qot), interface state density (Dit).
In the third part of this thesis, an improved electrical characteristics and low damage ultra-thin SiGe FinFETs were fabricated by application of sequential layer etching and high pressure annealing at low temperatures ranging from 500⁰C~600⁰C. SiGe FinFETs can effectively suppress junction leakage and therefore high ION/IOFF ratio (3.38 × 106 A/µm) at VD = -0.1V is achieved. sALE etched FinFET demonstrate less negative threshold voltage shift, an improved DIBL at lower fin width and an enhanced effective mobility and lower interface trap densities. DIBL is greatly influenced due to abrupt negative shift in threshold voltage for cALE FinFET and an improved case for sALE FinFET. DIBL for sALE is 130 mV/V & 172 mV/V for cALE at 40 nm fin width. Based on the understanding results, sequential layer etching can anisotropically etch down the vertical SiGe Fin structure with lower surface roughness. Furthermore, high pressure annealing was applied on fin structure to recover the damages caused during plasma continuous etching process. The lowest surface (RMS) of 0.17 nm was observed for sALE etched FinFET and the highest RMS of 0.28 nm was noted for cALE FinFET. The lowest subthreshold swing of 88 mV/dec was obtained at fin width= 40 nm & gate length= 100 nm for SiGe FinFET that is etched by sequential layer etching technique. Based on the result findings in this study, the sequential layer etching technique and high-pressure annealing has shown to be more reliable and successful than the continuous layer etching compared with MWA at high power approach for the fabrication of FinFET devices.

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