傳統立體匹配方式需要使用匹配視窗並且計算其中每一像素與中心點之間的權重進而計算整個視窗的匹配成本，如此一來會耗費大量運算時間，在硬體實現時也會耗費更多的資源，進而造成效率的降低。本論文提出一種快速立體匹配演算方式，使用三組一維疊代方式生成支援區域，取代傳統匹配視窗之方式以聚合匹配成本，大幅降低運算複雜度，並且更易於硬體架構的實現。
本演算法首先計算出由顏色普查式轉換後的位元串之間的漢明距離作為原始匹配成本，配合改良的適應性權重進行疊代式成本聚合後，再決定最佳視差進而得到初始深度圖，最後將邊緣及遭遮擋之區域做修補之後可得到更精確之結果。
同時，本論文也設計了對應演算法之硬體架構，並以Altera之 FPGA加以實現，此架構共需約27k個邏輯單元、78k個暫存器及約4.8Mb的記憶體儲存量，時脈最快可達160 MHz，提供解析度1920 × 1080、每秒60張且深度搜尋範圍為64層之處理速度。

Traditional local stereo matching methods, which require a window and its weights between the center pixel and neighboring pixels to compute matching cost, acquire more computation and consume more resources. Once they are implemented in hardware, the window-based aggregation decreases the efficiency. In this thesis, a fast local stereo matching algorithm is proposed by replacing window-based aggregation with three one-dimensional iterative aggregation processes to construct the effective support region. The iterative aggregation reduces complexity and is suitable for hardware realization.
The proposed algorithm computes raw matching costs with Hamming distances of bit-streams resulted from color census transform, then, uses modified adaptive support weights to perform iterative aggregations for estimation of best disparities. Refinement is used to repair error disparities in boundary and occluded regions.
Furthermore, the corresponding VLSI is provided and realized in Altera FPGA. The design requires 27k logic elements, 78k registers and 4.8Mb RAM, and the speed achieves 60 frames per second with 1920 × 1080 resolution and 64 disparity levels in 160 MHz.

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