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研究生: 黃威霖
Huang, Wei-Lin
論文名稱: 適合低電壓應用端的高效率 CMOS直流轉直流切換式穩壓器
A High Efficiency CMOS DC-DC Switching Voltage Regulator for Low Voltage Applications
指導教授: 郭泰豪
Kuo, Tai-Haur
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2004
畢業學年度: 92
語文別: 英文
論文頁數: 73
中文關鍵詞: 直流穩壓器
外文關鍵詞: regulator, DC
相關次數: 點閱:48下載:6
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  • 摘要
    本論文針對低電源電壓電子系統所需要的直流轉直流降壓切換式穩壓器提出設計與實現。這個交換式穩壓器在穩態時有很小的輸出電壓漣波,並且在負載突然改變時,有很快的暫態響應。它也具有很高的電能轉換效率並且適合可攜式電子系統產品來使用,例如:行動電話、數位相機等等、個人數位助理等等。
    為了要降低輸出電壓漣波以及暫態響應回復時間,此一切換式穩壓積體電路設計具有很高的操作頻率。除此之外,為了要達到快速的暫態響應,整個回授回路頻寬也盡可能地加寬。為了要使得電能轉換更有效率,此穩壓器以兩種操作模式來加強:PWM以及PFM,分別運用在重負載及輕負載的狀況。另外一個用來增加電能轉換效率的技術就是設計一個具有反穿透電流以及適應性閒置時間控制兩種功能的緩衝電路。這個技術可以防止穿透電流的發生必且減少體二極體在切換轉態時的導通時間。為了要消除在最初啟動時可能傷害在功率級的電子元件的突然增加的過大電流,柔性啟動操作模式也被設計在此晶片之中。
    此一穩壓晶片是透過財團法人國家實驗研究院晶片系統設計中心來製造,使用台灣積體電路製造股份有限公司所提供的0.35um 2P4M 3.3V/5V Mixed Signal CMOS 製造技術。此晶片的尺寸大約是1.5 x 1.5 mm2。其他相關的詳細效能將會在接下來的章節中描述。

    Abstract
    The design and implementation of a DC-DC buck
    switching regulator for low supply voltage electronic system is presented in this thesis. This switching regulator has low output ripple in steady state and fast transient response when the load is suddenly changed. It also has high power conversion efficiency that is suitable for portable electronic applications that are powered by batteries such as mobile phone, digital camera, PDA, etc.
    The switching regulator IC is designed with high operation frequency for reducing the output voltage ripple and the transient response recovery time. In addition, the feedback loop bandwidth is designed as wide as possible to achieve fast transient response. For making power conversion more efficient, the regulator is enhanced with two operation modes, PWM and PFM, for heavy and light load conditions. Another technique for increasing the power conversion efficiency is to design the buffer for driving the power MOSFET with the characteristics of anti-shoot through current and adaptive dead time control. This technique can prevent the occurrences of the shoot through
    current and reduce the body diode conduction time during switching transitions. To eliminate the excess large current at the start up of the regulator that may damage the devices of the power stage, the soft start operation is designed.
    This regulator IC is fabricated with TSMC 0.35um 2P4M 3.3V/5V Mixed Signal CMOS technology through CIC. The chip size is about 1.5×1.5 mm2. Other detailed performances will be described in the following chapters.

    Table of Contents Chapter 1 Introduction 1 1.1 Background and Review.....................1 1.2 Motivation................................3 1.3 Thesis Organization.......................4 Chapter 2 Fundamentals of Switching Voltage Regulator 5 2.1 Basic Power Stage Topologies..............5 2.2 Operational Principles of Buck Topology...6 2.3 Analysis of Feedback Loop Stability......11 2.4Specifications............................18 Chapter 3 System Architecture Design 22 3.1 System Blocks............................22 3.2 Soft Start Operation.....................24 3.3 PWM/PFM Operation........................25 Chapter 4 Circuit Implementation 28 4.1 Power Stage..............................28 4.2 Bias Circuit.............................30 4.3 Bandgap Voltage Reference................32 4.4 Error Amplifier..........................35 4.5 Sawtooth Oscillator......................38 4.6 PWM and PFM Modulators...................40 4.7 PWM/PFM Detector.........................41 4.8 Soft Start Circuit.......................42 4.9 Control Logic............................44 4.10 Zero Current Detector...................45 4.11 Anti-Ringing Switch.....................46 4.12 Anti-Shoot Through Buffer...............47 4.13 Simulation Results and Chip Layout......49 Chapter 5 Measurement 57 5.1 Measurement Setup........................57 5.2 PCB Layout Considerations................58 Chapter 6 Conclusions 59 6.1 Conclusions..............................59 6.2 Future Work..............................59 References 60

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