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研究生：	古光輝 Gu, Gaung-Hui
論文名稱：	泛在環境與具強健性之非文字相關語者辨識及SVM/SMO演算法之FPGA設計與實現 Ubiquitous and Robust Text-Independent Speaker Recognition and FPGA Implementation for SMO algorithm of SVM
指導教授：	王駿發 Wang, Jhing-Fa
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	75
中文關鍵詞：	語者辨識、支援向量機
外文關鍵詞：	SVM, Speaker Recognition
相關次數：	點閱：84 下載：4
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基於SVM分類之語者辨識，我們提出具有強健性之非文字相關語者辨識系統應用於泛場環境中。將6隻麥克風分佈在泛場環境來接收不同位置之聲源，發話的語者將不受麥可風距離之限制並可隨意走動。利用混合器(Mixer)將多隻麥克風所接收到的聲源混合成單一個音源，利用SNR-Aware Subspace Speech Enhancement技術來抑制泛場環境中的噪音，並以Multi-Class SVM取代傳統的GMMs分類方法來進行聲音的訓練及測試。由實驗結果得知，所提出之架構應用於泛場環境中辨識率高達97.2%。
再者，我們將SVM之SMO演算法依硬體電路平行計算特性，分割成六個STEP實現成硬體電路並以FPGA來驗證。提出了有效率的使用快取與節省一半以上快取空間的方法來減少Kernel Function計算的時間，以及實現與演算法相同的啟發式選擇之硬體電路用來減少SVM訓練時間，由PC上實驗結果，採用啟發式選擇可節省2.17倍以上的訓練時間。由FPGA驗證結果得知，使用快取比未使用快取的訓練時間可以減少53%，且應用於泛場環境中辨識率高達92.5%。

A novel architecture for ubiquitous and robust of text-independent speaker recognition based on SVM approach is proposed. In this architecture, multiple far-field microphones of configuration is adopted to receive the pervasive speech signals, and the distance effect between speaker and microphone is supposed to be ignored. Then the multi-channel speech signals are added together through a mixer. In a ubiquitous computing environment, the received speech signal is usually heavily corrupted by background noises. An SNR-aware subspace speech of enhancement approach is used as a pre-processing to enhance the mixed informational signal as well as suppressing the noise. Considering the text-independent speaker recognition, this proposed work applies multi-class support vectors machine (SVM) instead of using conventional Gaussian mixture models (GMMs). In our experiments, the speaker recognition rate up to 97.2% with the proposed ubiquitous architecture of speaker recognition system.
Additionally, we proposed a hardware realization of speaker identification system based on sequential minimal optimization (SMO) algorithm of SVM. We also proposed more efficient method of cache table utilization, and intend to save more then one half of cache table space as well as to reduce processing time of kernel function. Moreover, the heuristics selection method of SMO algorithm is implemented into hardware design to reduce the training time. In our experiments, the training time can reduce 2.17 times less than non-use of heuristics selection method on PC. And our finding shows that the identification ratio up to 92.5% of accuracy and reduced 53% of training time in hardware implementation.

CHAPTER 1  Introduction	1
1  Background	1
2  Related Work	3
3  Motivation	4
4  Thesis Organization	4
CHAPTER 2  Proposed Frameworks	5
1  System Overview	5
2  Speech Signal Pre-processing	5
2.1  End-Point Detector	5
2.2  Pre-Emphasis	6
2.3  Frame Block	6
2.4  Hamming Windows	7
3  SNR-Aware Subspace Speech Enhancement	7
4  Feature Extraction	8
4.1  Diversity Coefficients Tuning by MFCC	8
4.2  Order Selection for LPCC	9
5  Support Vector Machine Classification	10
5.1  Training and Testing Processes of Multi-class SVMs	13
5.2  Tuning of SVM Parameters	15
CHAPTER 3  FPGA Implementation for SMO Algorithm of SVM	16
1  Introduction to the Sequential Minimal Optimization (SMO)	16
2  Dividing SMO Algorithm into Six STEP for Hardware Implementation	20
3  The Proposed SMO Hardware Architecture Design	23
3.1  Fixed Point Format	25
3.2  The Design Method of STEP0	26
3.3  The Design Method of STEP1	26
          3.3.3.1  The Kernel Function and Learning Function Design Method	30
          3.3.3.2  Speed Up for Training Processes --- Heuristics Selection Method for Second  α	   31
3.4  The Design Method of STEP2	34
3.5  The Design Method of STEP3	36
3.6  The Design Method of STEP4	37
3.7  The Design Method of STEP5	38
          3.3.7.1  Speed Up for Kernel Function --- Using Cache Table for STEP5	42
          3.3.7.2  More Efficient Method of Cache Table Utilization	43
3.8  The Design Method of SMO Control Center (SCC)	47
CHAPTER 4  Experimental Results and Comparisons	52
1  Interdiction to Experimental Environment	52
2  PC Performance Evaluation	54
2.1  The GUI of Speaker Identification System	54
2.2  IMD Database Evaluation Result	55
2.3  SMD Database Evaluation Result	58
2.4  FMMD Database Evaluation Result	61
2.5  Experimental Comparison	63
3  The FPGA Performance Evaluation	63
3.1  Interdiction to Field-Programmable Gate Array (FPGA)	63
3.2  Overall Hardware and Software Simulation of SMO Processes	65
3.3  Experimental Results	66
3.3.1  LPCC Evaluation Result	66
          4.3.3.2  MFCC Evaluation Result	69
3.4  A Comparison of Hardware Implementation with Related Work	69
CHAPTER 5  Conclusion and Feature Work	71
Reference	72
                                    

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校內：2009-08-05公開
校外：2009-08-05公開

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