首先，我們在本論文中提及了一個完整實現的記憶體子系統。其所屬的平台是先前本實驗室開發的特製通用繪圖處理器(General purpose GPU)架構。為了能夠快速開發與實現這樣的晶片，在早期設計階段我們將先前的C++語言模擬器版本做時序上的延伸探討，盡力保持完整詳細的記憶體流量模擬與快速的模擬時間。這是由於記憶體流量佔程式模擬時間的大部分。例如，第一層快取記憶體(Cache)的存取要求送上晶片網路系統(NoC)會經歷非定值的延遲時間，記憶體快取一致性與記憶體排程器的選擇等皆會影響架構核心所見的延遲時間。而關於記憶體空間分配的方法我們也探討了粗與細兩種不同粒度的分散方法。在晶片網路模組我們也探討了網格狀架構(Mesh)在幾何特性上強韌的原因並採用此類拓樸。
本篇論文另一個特點是採用機器學習的效能預測模型。使用kmeans與SVM兩種模型可以分析出各別測試程式在所有可能的硬體架構設定下，於何種參數數值下會有最佳效能結果。於此，還能進一步預測未測試過的程式將會在何硬體參數下達到最高效能。Kmeans演算法負責將所有測試程式的效能結果分類為若干種特性相似的群集，做為預測模型的參考範本。SVM模型則接著以記憶體系統相關的量測結果訓練出最終的預測參數。由於我們宣稱程式效能主要由記憶體子系統所影響，只以此類特徵分析的結果在八個群集設定下可以達到至少有46.48%的測試點落在百分之十以內的錯誤率；在改變群集數量的量測中，最高可以有57.97%的測試點落在百分之十以內的錯誤率。最終，我們發現最佳的效能結果不一定發生在給定最大硬體資源數量上，這是由於晶片網路系統上的交通流量時常有塞車的情況而影響。
結合了記憶體子系統的開發與預測模型，我們旨在提供一套可靠且精確的早期開發平台，使往後的晶片實現能夠採用現階段的效能探討並快速的完成。

In this thesis, we present a memory subsystem of customized general purpose GPU architecture. For fast development, the C++ simulated architecture should be kept as light-weight while timing accurate at the same time. Since most parts of benchmark simulation time come from memory subsystem-related latencies. For example, the level one cache miss will trigger Network on Chip (NoC) traffic; the cache coherence and memory controller scheduling policy also affect the latency viewed by streaming multiprocessor in this GPGPU architecture. Also, we discuss the memory space partitioning methods in one following section including coarse grain and fine grain partitioning methods. As for NoC module, we adopted previous research in this work and discuss geometry features of chosen topology – Mesh structure for robust reason.
Another contribution of this work is that two machine learning models are used for predicting architecture performance and depicting the performance trend across plenty of hardware configuration settings. We aim to guess a reasonable summit value in performance surface by the following procedures. First, kmeans algorithm clusters training benchmarks into determined number of clusters. The multi-class Support Vector Machine (SVM) model is latter trained to fit memory-related only features. During validation phase, testing benchmarks’ summit performance values are predicted by the result from training phase. Under eight clusters setting, 46.48% predicted cycle performance counts across all tested benchmarks are less than 10% error comparing to real performance values. By varying the number of clusters, up to 57.97% points are less than 10% errors. Also, we show that summit performance not necessary happen under maximum hardware resources. Some discussions point out the memory traffic issues that significantly drag down the execution speed of certain accessing patterns from benchmarks.
Combined the mentioned contributions together, we aim to provide a reliable and accurate early stage simulation platform for future IC chip implementation in an efficient way.

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