| 研究生: |
郭信宏 Kuo, Hsin-Hung |
|---|---|
| 論文名稱: |
應用於802.11 WLAN 之2GHz 及5GHz CMOS 頻率合成器RFIC 之設計研究 Research on 2GHz and 5GHz CMOS Frequency Synthesizer RFICs For 802.11 WLAN |
| 指導教授: |
莊惠如
Chuang, Huey-Ru |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2004 |
| 畢業學年度: | 92 |
| 語文別: | 中文 |
| 論文頁數: | 100 |
| 中文關鍵詞: | 頻率合成器 |
| 外文關鍵詞: | frequency synthesizer |
| 相關次數: | 點閱:76 下載:10 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文以TSMC 0.25um 1P5M及0.18um 1P6M CMOS製程,設計研究應用於802.11 WLAN之Integer-N頻率合成器RFIC,包含相頻偵測器、電荷幫浦、壓控振盪器及pulse-swallow counter。RFIC晶片採用打鎊線至FR-4基板上進行量測,晶片均預留PAD以單獨量測L-C tank壓控振盪器及pulse-swallow counter。壓控振盪器之設計上利用電晶體開關切換電容,使L-C tank的電容值在開關切換前後有一定程度的變化,以克服製程偏移所造成頻率偏差的影響。5GHz L-C tank壓控振盪器 (0.25um)輸出頻率在switch on時為4780~4943MHz,switch off時為4877.3~5022.3MHz,相位雜訊為-85.6dBc/Hz@100KHz;5GHz L-C tank壓控振盪器 (0.18um)輸出頻率在switch on時為4598.3~4723.7MHz,switch off時為4739.3~4858.5MHz,相位雜訊為-86.4dBc/Hz@100KHz。2GHz L-C tank壓控振盪器 (0.25um)輸出頻率為1808~1970MHz,相位雜訊為-95.1dBc/Hz@100KHz。5GHz pulse-swallow counter (0.18um)最高可操作頻率約為5.5GHz;2GHz pulse-swallow counter (0.25um)最高可操作頻率約為2.8GHz。完成之5GHz與2GHz頻率合成器晶片之量測與部份操作功能特性及發生之問題,均有完整之討論。
This thesis presents the research on CMOS integer-N frequency synthesizer RFICs for 2GHz and 5GHz 802.11 WLAN applications. The RFICs are fabricated in a TSMC standard 0.25um and 0.18um CMOS process. A switching capacitor mechanism is used in the design of VCO to change the capacitance of the LC tank to compensate the frequency deviation due to process variation. The circuit measurement is performed using a FR-4 PCB test fixture. The 5GHz 0.25-um CMOS VCO exhibits an output frequency from 4780 to 4943MHz (switch on) and 4877.3 to 5022.3MHz (switch off), respectively, and the phase noise is –85.6dBc/Hz@100KHz. The 5GHz 0.18-um CMOS VCO exhibits an output frequency from 4598.3 to 4723.7MHz (switch on) and 4739.3 to 4858.5MHz (switch off), respectively, and the phase noise is –86.4dBc/Hz@100KHz. The 2GHz 0.25-um CMOS VCO has an output frequency from 1808 to 1970 MHz with a phase noise of –95.1dBc/Hz@100KHz. The 5-GHz pulse-swallow counter (0.18um) exhibits a maximum operation frequency of about 5.5GHz. The 2-GHz pulse-swallow counter (0.25um) exhibits a maximum operation frequency of about 2.8GHz. Detail measurement and the frequency synthesizer performance problem is presented and discussed.
[1] J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design, Kluwer Academic Publishers, Boston USA, 1998.
[2] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill companies, New York USA, 2001.
[3] Avanindra Madisetti, Alan Y. Kwentus, and Alan N. Willson, “A 100-MHz, 16-b, Direct Digital Frequency Synthesizer with a 100-dBc Spurious-Free Dynamic Range”, IEEE J. Solid-State Circuits, vol. 34, no. 8, August 1999.
[4] 袁杰,高頻通信電路設計,1994。
[5] William F. Egan, Pratical RF System Design, John Wiley & Sons, 2003.
[6] B. Razavi, RF Microelectronics, Prentice Hall, 1997.
[7] 于宗仁,應用在HDTV/ITV寬頻帶射頻調諧器及900-MHz/2.4GHz無線通訊之頻率合成器的設計,國立成功大學電機工程研究所碩士論文,民國八十六年。
[8] A. Hajimiri and T.H. Lee,“Oscillator phase noise: a tutorial,” IEEE J. of Solid-State Circuits, vol.32, No. 3, pp. 326 -336, March 2000.
[9] 林昂生,應用在數位音訊廣播(DAB)接收機L頻帶降頻器之CMOS單晶射頻微波積體電路,國立成功大學電機工程研究所碩士論文,民國九十年
[10] 廖哲宏,應用於IEEE 802.11a WLAN之5.7GHz CMOS 射頻接收機及功率放大器RFICs,國立成功大學電機工程研究所碩士論文,民國九十二年
[11] Mozhgan Mansuri, Dean Liu, and Chih-Kong Ken Yang, “Fast Frequency Acquisition Phase-Frequency Detectors for Gsamples/s Phase-Locked Loops”, IEEE J. Solid-State Circuits, vol. 37, no. 10, October 2002.
[12] June-Ming Hsu et al., “Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application”, IEEE Transactions on Circuits and Systems, vol. 48, no. 9, September 2001.
[13] A. Djemouai, M. Sawan, “Fast-Locking Low-Jitter Integrated CMOS Phase-Locked Loop”, IEEE International Symposium on Circuits and Systems ISCAS, pp. 264-267, May 6-9, 2001.
[14] Robert C. Chang and Lung-Chih Kuo, “A New Low-Voltage Charge Pump Circuit for PLL”, IEEE International Symposium on Circuits and Systems ISCAS, pp.701-703, May 28-31, 2000.
[15] David A. Johns and Ken Martin, Analog Integrrated Circuit Design, John Wiley & Sons, 1997.
[16] Ching-Yuan Yang et al., “New Dynamic Flip-Flops for High-speed Dual-Modulus Prescaler”, IEEE J. Solid-State Circuits, vol. 33, no. 10, October 1998.
[17] Sang-Hoon Lee and Hong June Park, “A CMOS High-Speed Wide-Range Programmable Counter”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 9, September 2002.