在類比CMOS IC設計流程中，實體層的設計佔有重要的地位。良好的實體層設計必須具有對數位雜訊及製成波動低敏感的特性，所以類比的實體層設計一直都還是相當耗時以及用手畫的工作。由於超大型積體電路(VLSI)複雜度的增加以及單晶片(SOC)的發展使得必須要有電腦輔助設計(CAD)來加速整個設計過程，對類比電路實體層設計而言，更需要有電腦輔助設計來改善它。
在本論文中，我們提出一個工具去自動化類比的實體層設計並同時加入類比電路的基本考量(元件的匹配、對稱及訊號線間的雜訊偶合效應)，此工具涵蓋的範圍包括從元件的產生到其區塊間的佈局及繞線。首先我們提供模組產生器將分割好的電路敘述檔根據元件匹配的考量轉換成其相對應的實體層，然後佈局工具依據對稱、導線長度及晶片面積的限制將所有的模組擺放至適當的位置。我們基本的繞線理論是使用找尋不跨過障礙物的最短路徑演算法，然後我們提出一個方法來避免吵雜的訊號線把雜訊偶合到抗雜訊低的訊號線。根據實驗結果，我們提出的工具可以在合理的時間內根據使用者訂定的限制來產生適合的類比電路實體層，因而使得整個類比電路實體層的設計更加有效率。

Layout design is a very important step in the analog CMOS IC design flow. Good layout quality should feature low susceptibility to digital noise and low sensitivity to process variation. It has historically been a time-consuming, manual task. The fast growth of complexity of VLSI systems and recent advances in System-On-Chip (SOC) developments, make it necessary to have powerful Computer-Aided-Design (CAD) tools to speed up the design process. This issue is especially important for analog circuit layout design.
In this thesis, we present a tool to automate analog layout design with analog basic considerations (matching, symmetry, and noise coupling). It covers from device level module generation to block level placement and routing. Fist, we provide a module generator to transfer partitioned netlists to physical layout with matching consideration. Placement tool then places all cells with symmetric, wire length, and area constraints. Obstacle-avoiding shortest finding algorithm is used for our basic routing algorithm and we propose an approach to avoiding noise coupling between noisy and sensitive nets. According to experimental results, our tool can handle analog circuit layout with user specified constraints in the reasonable time and make analog layout design more efficient.

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