鎖相迴路被廣泛的運用在各種系統中，以達成頻率合成、時脈/數據回復、時脈差異消除、、、等等的目的。目前已經有許多種不同架構的PLL被提出以及應用，但大多數所使用的PLL都屬於數位鎖相迴路，然而隨著積體電路技術的進步，現今的製程環境越來越適合數位電路的發展。數位設計可以有效率的將設計移轉至不同製程平台上，進而減少系統重新設計所需的時間，並且可以繼承數位電路有較高抗雜訊能力的優點。
本論文提出一延襲二階數位鎖相迴路頻率響應及穩定度特性之全數位鎖相迴路架構，將原本數位鎖相迴路中之類比電路全部改成數位電路，藉以將傳統的數位式鎖相迴路架構中，必須使用到電容及電阻的類比低通濾波器替換成不須要電容電阻的數位濾波器，減小電路佈局面積，亦減小加入電容電阻後所產生的不精確性，並且將電壓控制震盪器換成對雜訊較不敏感的數位控制振盪器，增加電路的穩定性。本電路為一個不須要像現有的全數位鎖相迴路，需要額外輸入一高頻訊號，或是需要複雜的演算法，而是一個與數位鎖相迴路架構類似，在經由簡單的計算過程分析頻率響應以及穩定度，得到所需要的參數之後，即可完成之全數位鎖相迴路。
研究晶片是透過國家晶片系統設計中心提供的製程服務，使用台灣積體電路公司0.18μm 1P6M 1.8V混合訊號製程，以32 S/B封裝，尺寸為0.759 x 0.954 mm2。量測結果驗證了本論文提出的架構之可行性。

The phase-locked-loop (PLL) is widely used in different applications, such as frequency synthesis, clock/data recovery, and clock de-skewing. Presently, the most designs of the PLL are digital PLLs which have analog loop filter and oscillator in their circuits, but with the advances in integrated circuit (IC) technology, the fabrication processes is more and more suitable for digital designs. A digital design is scalability and easy redesign with process changes or shrinks. Moreover designing an all-digital PLL can inherent noise immunity of digital circuits.
This paper presents an All-Digital Phase-Locked Loop (ADPLL) which inherits the frequency response and stability characteristics of the analog prototype PLL. Replacing the conventional RC loop filter with an all digital loop filter can decrease the layout area and eliminate the requirements of resistor and capacitor. Moreover, the analog voltage-control oscillator (VCO) is replaced by the digital control oscillator (DCO) in order to enhance the noise immunity. Therefore, this digital architecture can be easily redesign by analyzing the frequency response and stability.
The die area of the proposed chip is 0.759 x 0.954 mm2. The chip was implemented by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V process, patronized by National Chip Implementation Center (CIC). The measured results verify the effectiveness of this architecture.

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