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研究生：	陳卓凡 Chen, Cho-Fan
論文名稱：	管線式類比至數位轉換器之內建自我診斷電路 Built-In Self Diagnosis of Pipelined A/D Converters
指導教授：	張順志 Chang, Soon-Jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	69
中文關鍵詞：	管線式、類比至數位轉換器、診斷電路
外文關鍵詞：	pipelined, A/D converters, diagnosis circuits
相關次數：	點閱：130 下載：6
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本篇論文的主要目的是設計一個每秒取樣50百萬次8位元的管線式類比至數位轉換器及其內建自我診斷電路。此管線式類比至數位轉換器的操作電壓為3.3V，且此管線式類比至數位轉換器的每一管線式級(pipelined stage)的輸出電壓為1.15 伏特至 2.15 伏特。在此內建式自我診斷電路中，我們設計一個待測級保持器(Stage-Under-Test holder)去保持要測的管線式級的輸出電壓，然後將此電壓經過電壓控制震盪器(VCO)和數位電路，將電壓轉成數位碼。我們使用此數位碼來表示每一管線式級的輸出電壓，所以，可以利用這些數位電路去診斷管線式類比至數位轉換器內部電路的錯誤。為了驗證這個架構，我們注入電容不匹配的錯誤到待測級中來證明診斷架構的功能。
在這個診斷電路中，除了VCO，我們使用的電路都屬於數位電路，一般來講，高解析度的類比電路在低供應電壓下很難設計，所提的診斷電路大多是以數位電路完成，所以，為了達到高解析度會比用類比電路容易。在此診斷架構中，可消除待測級保持器所產生的偏差，並且幾乎不會影響到該類比至數位轉換器的效能。我們所有的電路設計與模擬，採用台積電 0.35微米 2P4M的製程檔案。

The main purpose of this thesis focuses on the design and diagnosis of a 50 MHz 8-bit pipelined ADC. The supply voltage of this ADC is 3.3 V and the output voltage range of each pipelined stage is from 1.15 V to 2.15 V. In the proposed Built-In Self Diagnosis circuit, we design a Stage-Under-Test Holder (SUT-Holder) to hold the output voltage of the selected pipelined stage. Then, the analog voltage of SUT is transformed into digital code by a voltage controlled oscillator (VCO) and a counter. By using the obtained digital codes to represent corresponding voltages of the pipelined stage, we can use simple digital circuits to diagnose errors in the pipelined stage. To verify this architecture, we inject faults of capacitor mismatch into SUTs to demonstrate the effectiveness of the proposed diagnosis scheme.
Except the VCO, all the employed building blocks of the diagnosis scheme are digital circuits in this work. Generally, design of analog circuits with high resolution is very difficult under low supply voltage. The proposed diagnosis circuit is mostly accomplished with digital circuits. So, it is much easier to achieve higher resolution than using pure analog circuits. The offsets induced by the SUT-Holder can be cancelled in the proposed diagnosis circuit. Also, the performance degradation of the ADC caused by the added circuits is very small. All circuit designs and simulations are based on TSMC 0.35m 2P4M process model.

Abstract..........II

Acknowledgement..........IV

Table of Contents..........V

List of Tables..........IX

List of Figures..........X

Chapter 1 Introduction..........1

1 Motivation..........1

2 Applications of Pipelined ADCs..........3

3 Organization of Thesis..........5

Chapter 2 The Basic Concept of Pipelined A/D Converters and the BIST for A/D
        Converters..........7

1 Introduction..........7

2 Parameters in ADCs..........7

2.1 Resolution..........7

2.2 INL..........8

2.3 DNL..........8

2.4 Missing Code..........8

2.5 Dynamic Range..........8

2.6 SNDR..........8

2.7 SFDR..........9

2.8 SNR..........9

3 Pipelined ADC Building Blocks..........10

4 Pipelined Stage Accuracy Requirements..........13

5 Selecting Stage Resolution..........15

6 Error Sources in Pipelined Stages..........17

6.1 Thermal Noise..........17

6.2 Comparator Offsets..........18

6.3 Non-ideal DAC Reference Level..........19

6.4 Stage Gain Error..........19

7 Digital Error Correction Technique..........20

8 Background to BIST..........21

8.1 BIST Implementations..........21

8.2 The Goal of BIST..........22

9 Testing Methods for ADCs..........23

9.1 Histogram Test Technique..........23

9.2 Self Calibrated ADC BIST..........24

9.3 MDAC and Stage Testing for Pipelined ADCs..........24
  
9.4 Two Comparators Testing of Pipelined ADCs..........25

10 Summary..........26

Chapter 3 Design of a 50MHz 8-Bit Pipelined A/D Converter..........27

1 Introduction..........27

2 1.5-bit / stage System Architecture of Pipelined ADC..........27

3 Circuit Design and Simulation..........	29

3.1 Required OPAMP Spec. in This Pipelined A/D Converter..........29

3.2 OPAMP..........30

3.3 Component Blocks in the Pipelined ADC..........34

          3.3.3.1 S/H..........34

          3.3.3.2 Sub-ADC..........35

          3.3.3.3 MDAC..........38

          3.3.3.4 Clock Generator..........39

          3.3.3.5 Synchronous Cell..........40

          3.3.3.6 Digital Error Correction..........40

4 Summary..........40

Chapter 4 Design of Diagnosis Circuits for a Pipelined A/D Converter..........43

1 Introduction..........43

2 VCO-Based Diagnosis..........44

2.1 VCO-Based Diagnosis Method..........44

2.2 VCO..........45

3 Blocks and Methodology of VCO Based Diagnosis..........47

3.1 Methodology..........47

3.2 SUT-Holder..........51

3.3 Clock Generation in VCO Based Diagnosis..........52

4 Diagnosis Architecture..........53

4.1 Whole Pipelined ADC Diagnosis..........53

4.2 Sub-ADC Testing..........55

5 Diagnosis Simulation Result..........56

5.1 Single Stage..........57

5.2 Whole Pipelined ADC..........58

5.3 Performance Simulation of DUT in the Diagnosis Architecture..........61

6 Summary..........62

Chapter 5 Conclusions and Future Work..........63

1 Conclusions..........63

2 Future Work..........64

References..........65

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校內：2009-02-01公開
校外：2010-02-01公開

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