類比電路自動化一直是大家希望解決的問題。之前研究類比電路自動化的論文，大多數以考慮擺置問題為主，很少考慮後續繞線問題，即使有在擺置階段考慮繞線的論文，其所使用的方法，都是直接套用數位電路考量可繞度的方法來預估繞線路徑，然而由於數位電路與類比電路考量的狀況並不完全一樣，因此直接套用其方法，可能會造成預測與實際產生很大的誤差。因此針對這些問題，在本論文中我們提出了一個最短路徑估量方法，用來決定模組與模組之間必須預留多大的繞線空間，才能同時滿足繞線與設計規則;同時，我們也提出了一個繞線的流程，可以完成所有的繞線包含訊號線和電源線。我們將此方法確實實現出來，從實驗的結果顯示，我們所設計的工具可以快速的完成電路佈局圖，並且實驗的結果顯示，我們所提出估量可繞度的方法與使用數位電路常用的估量方法相比，在所有測試電路皆可以得到較小的佈局圖面積與繞線的線長，而且也還能滿足設計規則的規範。

In past few years, analog design automation has attracted more attention, and many researches have been published. Most of them focus on placement of analog blocks without considering routing issues. Recently, some papers start to consider routability-driven placement in analog circuits. However, their models used to estimate routing congestion are based on approaches for digital circuits, which make routing paths estimated by their models not match to real routing paths. Hence, this thesis proposes a shortest path estimation model to predict routing channels between any two modules during placement stage. Moreover, DRC rules are considered in placement methodology in order to obtain legal layouts. In addition to placement, a routing methodology used to route nets, which include signal nets and power nets, is proposed. We actually implement the design flow as a tool. The experimental results show our tool can generate layouts efficiently. More importantly, our tool gets better results in term of area and wirelength in all test cases comparing to the method which uses the bounding box estimation method.

[1] F. Balasa and K. Lampaert, “Module placement for analog layout using the sequence-pair representation,” in Proc. DAC, 1999, pp. 274-279.
[2] P.-Y. Chou, H.-C. Ou, and Y.-W. Chang, “Heterogeneous B*-trees for analog placement with symmetry and regularity considerations,” in Proc. ICCAD, 2011,
pp. 512-516
[3] C. Y. Lee, “An algorithm for path connections and its applications,” IRE Trans. Electron. Comput., vol. EC-10, pp. 346- 365, Sept. 1961.
[4] J.-M. Lin, G.-M. Wu, Y.-W. Chang, and J.-H. Chuang, “Placement with symmetry constraints for analog layout design using TCG-S,” in Proc. ASP-DAC, 2005, pp. 1135- 1138.
[5] P.-H. Lin and S.-C. Lin, “Analog placement based on novel symmetry-island formulation,” in Proc. DAC, 2007, pp.465-470.
[6] P.-H. Lin, H. Zhang, M. D. F. Wong, and Y.-W. Chang, “Thermal-driven analog placement considering device matching,” in Proc. DAC, 2009, pp. 593-598.
[7] C.-W. Lin, J.-M. Lin, C.-P. Huang, and S.-J. Chang, “Performance-driven analog placement considering boundary constraint,” in Proc. DAC, 2010, pp. 292-297.
[8] C.-W. Lin, C.-C. Lu, J.-M. Lin, and S.-J. Chang, “Routability-driven placement algorithm for analog integrated circuits,” in Proc. ISPD, 2012 pp. 71-78.
[9] P.-H. Lin and S.-C. Lin, “Analog placement based on novel symmetry-island formulation,” in Proc. DAC, 2007, pp. 465-470.
[10] Y. Pang, F. Balasa, K. Lampaert, and C.-K. Cheng, “Block placement with symmetry constraints based on the O-tree non-slicing representation,” in Proc. DAC, 2000, pp. 464-
467.
[11] P.-H. Wu, P.-H. Lin, Y.-R. Chen, B.-S. Chou, T.-C. Chen, T.-Y. Ho, and B.-D. Liu, “Performance-driven analog placement considering monotonic current paths” in Proc. ICCAD, 2012, pp. 613-619.
[12] L. Xiao, E. F.Y. Young, X. He, and K.P. Pun, “Practical placement and routing techniques for analog circuit designs,” in Proc. ICCAD, 2010, pp. 675-679.