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研究生：	趙億智 Chao, Yi-Chih
論文名稱：	用於H.264/AVC去方塊濾波器之高產能與資料再用架構 A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filters
指導教授：	劉濱達 Liu, Bin-Da 楊家輝 Yang, Jar-Ferr
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	83
中文關鍵詞：	濾波器
外文關鍵詞：	filter
相關次數：	點閱：66 下載：1
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　　本碩士論文中，我們實現出一個適用於H.264/AVC去方塊濾波器之高產能與資料再用架構。為了能加速濾波的速度，我們使用改善過後的濾波順序，在這個方式下，需要兩個暫存器矩陣以達到資料再用的效果。我們採用特殊的排列方式來編排記憶體中的像素，此方式可以不需額外時間，來完成水平和垂直方向的濾波。在一維濾波器的設計上，為了達到較好的效能，我們根據架構的特性，做兩級管線化的處理，也根據濾波的特性，以較小的面積來實現電路。在完整的架構中，總共需要兩個記憶體，一個是144×32位元的單埠記憶體，另一個是16×32位元的雙埠記憶體。

　　在實現的數據中，我們可以得知總共需要16,600個邏輯閘，在佈局的實現上，總共的面積為184,900 μm2。然而，當我們要針對一個巨大區塊(macroblock)做濾波時，總共需要228個時脈週期數。整個架構可以達到的最大操作頻率為100 MHz，換言之，當時脈操作在85 MHz的頻率下，我們可以即時地針對4XGA (2048×1536)影像大小的畫面，且成功地實現去區塊濾波過程，而且此時的影像是以每秒30張畫面的方式撥放。

　　In this thesis, we propose a high throughput and data reuse architecture of de-blocking filters for H.264/AVC. We modify the filtering order to speed up the deblocking filter processes. With this filtering order, there are two 4×4 register arrays needed for data reuse. In the arrangement of pixels in SRAMs, the GOP format is designed to achieve the fast access pixels instead of COP or ROP methods. Further, the two pipelined stages are realized in 1-D filter, and the fewer logic gate counts are implemented according to the characteristics of de-blocking filter processes. There are two SRAMs, 144×32 bits single-port SRAM and 16×32 bits two-port SRAM, exploited in this design.

　　The simulation results show the total number of logic gate counts is 16.6k, and the core size of layout is 184,900 μm2. However, it needs 228 clock cycles to de-block one macroblock. This proposed architecture can be achieved with the clock frequency at 100 MHz. In other words, it can process the real-time deblocking of 4XGA (2048×1536) picture with 30 frames per second when the clock frequency is set to 85 MHz.

Table of Contents	                                  i
Acknowledgement	                                  iii
Abstract	                                           iv
List of Figures	                                  vi
List of Tables	                                  viii

Chapter 1 Introduction	                         1
1.1 Motivation	                                  1
1.2 Organization for the Thesis	                3

Chapter 2 Basic Concepts of Video CODEC and Overview of  H.264/AVC Video Coding Standard	                                           4
2.1 Basic Concepts for Video Coding	                4
2.2 Overview of H.264/AVC Video Coding Standard     8
2.2.1 Variable Block Size	                        10
2.2.2 Intra Prediction	                        11
2.2.3 Integer Transform	                        12
2.2.4 In-loop De-blocking Filter	               14
2.2.5 Entropy Coding	                        15

Chapter 3 Classification of De-blocking Filters and H.264/AVC  De-blocking Filter	                                           17
3.1 Blocky Artifact	                         18
3.2 Difference between Post-processing and In-loop Filters	19
3.3 Boundary Strength and Filtering Order in H.264/AVC	         22
3.4 Derivation of Threshod Variables	                           27
3.5 Filtering Process	                                     34
3.5.1 Edges with BS less than 4	                            34
3.5.2 Edges with BS equal to 4	                            36

Chapter 4 Proposed Architecture for H.264/AVC De-blocking Filter	38
4.1 Overview of Related Research	                            39
4.2 Memory Arrangement and Organization	                   40
4.3 Modified Filtering Order	                            43
4.4 One Dimensional De-blocking Filter	                   44
4.4.1 Edges with BS less than 4	                            45
4.4.2 Edges with BS equal to 4	                            48
4.5 Entire De-blocking Filter Architecture	                   54

Chapter 5 Simulation Results and Verification	                   59
5.1 Simulation Results and Comparisons	                   59
5.2 Verification	                                              62
5.3 Summary	                                              73

Chapter 6 Conclusions and Future Works	                   74
6.1 Conclusions	                                               74
6.2 Future Works	                                              75
References	                                              77
Publications	                                              81
                                    

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校內：2007-07-27公開
校外：2007-07-27公開

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