隨著半導體製程的演進，在二維晶片做電路設計遇到越來越多的挑戰，因此越來越多人將三維晶片視為是突破瓶頸的解決方案，其中平面規劃在三維晶片實體設計依然扮演很重要的角色。近年來隨者行動裝置的普及和熱門，消費者越來越重視電力續航之問題，因此發展低功耗的晶片已成為晶片設計中的重要議題。隨者晶片設計中的模組數量增多，晶片的功率密度(power density)更勝以往，造成晶片中動態功率消耗和漏電流功耗等問題更加嚴重，許多用來降低晶片功率消耗的方法相繼被提出，其中多重電壓源是解決此問題的有效方法之一。
過去鮮少有針對三維平面規劃同時考量多重電壓源的相關研究，因為多重電壓源的平面規劃比起傳統平面規劃複雜許多，它不僅需要盡量將相同電壓域的模組擺置在鄰近區域以形成一個電壓島來降低電源繞線的複雜度，同時還必須考量訊號線的繞線長度，並且滿足固定框架的限制。本研究提出了一個可以處理多重電壓島之三維平面規劃演算法流程，透過我們的方法所產生的平面規劃，可以有效減少電源規劃階段所需的繞線資源同時減少電路的電壓衰退。

Several recent studies show that 3D ICs offer significant power savings and higher device density over 2D ICs. Hence, developing a floorplanner which can consider different issues for 3D ICs becomes more and more important. Low power is one of the key driving forces in semiconductor industry. To reduce power consumption, multiple supply voltages (MSVs) is one of the most effective techniques which is widely applied in real designs. However, to implement MSVs in 3D ICs will make floorplanning become more complex. Thus, this research proposes a voltage-island driven fixed-outline floorplanning methodology for 3D ICs. In addition to wirelength consideration, modules in the same voltage domain will be placed in close regions for facilitating power planning. Moreover, the fixed-outline constraint is satisfied. Hence, IR-drop violation and power delivery network (PDN) resource usage can be optimized simultaneously.

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