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研究生： 傅俊輝
Fu, Jun-Hui
論文名稱： 一個適用於卷積神經網路之電荷重新分佈式記憶體內運算加速器
A Charge Redistribution Based Computing-in-Memory Accelerator for Convolutional Neural Networks
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 115
中文關鍵詞： 記憶體內運算 、靜態隨機存取記憶體 、神經網路 、電荷重新分佈 、類比運算
外文關鍵詞： computing-in-memory (CIM), static random access memory (SRAM), neural network (NN), charge redistribution, analog computation
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    • 本論文提出一個適用於卷積神經網路之電荷重新分佈式記憶體內運算加速器。此晶片採用了八顆電晶體之靜態隨機存取記憶體，其去耦合讀取埠可避免資料誤寫入且可使用類比式運算進一步降低神經網路中算術運算所需的能量，以降低功率消耗。此外，為了提升能源效率，提出了兩個技巧：第一個技巧為不同權重電容切換的方式，其比常見的電流充放電方式具有較佳的線性度，且能降低類比數位轉換器的數量；第二個為低乘加值跳越的方式，藉由跳過前幾個位元的類比數位轉換，以增加運算速度及降低功率消耗。
    本設計以台積電40奈米CMOS標準1P9M製程實作測試晶片，整體晶片面積為2.421 mm2，其中核心電路占整體的18.24%。測試結果顯示在輸入電壓0.9伏特及一億赫茲時脈下，本晶片在MNIST與CIFAR-10資料集的Top-1準確率可分別達99%與91%，而換算出來的能源效率為3.7 TOPS/W，使用提出的低乘加值跳越技巧，可達到9.88 TOPS/W；在輸入電壓0.7伏特及八千萬赫茲時脈下，能源效率為5.1 TOPS/W，使用提出的低乘加值跳越技巧，最高可達到12.02 TOPS/W。

    This thesis presents a charge redistribution based computing-in-memory (CIM) accelerator for convolutional neural networks (CNNs). This CIM macro adopts 9T static random access memory (SRAM) with a read-decoupled port to avoid read-disturbing and perform the analog computation for further diminishing the energy consumption per arithmetic operation. A weighted capacitor switching technique is proposed to achieve a better linearity performance than conventional current charging/discharging scheme and reduce the number of analog-to-digital converters (ADC). Moreover, a low multiply-accumulate (MAC) value skipping technique is also proposed to enhance the speed and reduce the power consumption of the CIM macro by skipping the first few bits during the analog-to-digital conversion.
    The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS standard 1P9M technology, where the chip covers an area of 2.42 mm2, and the core circuit accounts for 18.24% of the total area. The measurement result shows that the top-1 accuracies of MNIST and CIFAR-10 are 99% and 91% with a supply voltage of 0.9-V and a clock frequency of 100-MHz, respectively. The equivalent energy efficiency is 3.7 TOPS/W, and could achieve 9.88 TOPS/W with the proposed low MAC value skipping technique. In addition, the prototype could achieve 5.1 TOPS/W with a supply voltage of 0.7-V and a clock frequency 80-MHz. With the proposed low MAC value skipping technique, the energy efficiency could obtain at most 12.02 TOPS/W.

    摘 要 I Abstract II List of Tables VIII List of Figures IX Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Computing-in-Memory 3 1.3 Thesis Organization 5 Chapter 2 Basics of Neural Networks and Data Management 6 2.1 Fundamentals of Deep Neural Networks 7 2.2 Overview of Convolutional Neural Network 12 2.2.1 Basics of Convolutional Neural Networks 12 2.2.2 Non-Linear Activation Function 13 2.2.3 Pooling Function 15 2.2.4 Normalization Function 16 2.3 Quantization of Neural Networks 16 2.3.1 Linear Quantization 18 2.3.2 Non-Linear Quantization 21 2.3.3 Quantization-Aware Training 22 2.4 Introduction to Data Management 24 2.4.1 Dataflow 24 2.4.2 Data Reuse 30 Chapter 3 Fundamentals of Computing-in-Memory 33 3.1 Introduction to Computing-in-Memory 34 3.1.1 Concept of Computing-in-Memory 34 3.1.2 Structure of Computing-in-Memory 36 3.2 Digital-to-Analog Conversion 38 3.2.1 Basic concept of DAC 39 3.2.2 Static Specifications of DAC 42 3.2.3 Implementation of DAC 45 3.3 Mixed-Signal Computation in SRAM 48 3.3.1 6T SRAM Bit-cell 49 3.3.2 Charge-Based Multiplication and Accumulation 53 3.4 Analog-to-Digital Conversion 55 3.4.1 The Concept and Operation of SAR ADC 56 3.4.2 Quantization Error 62 3.4.3 Static Specifications of ADC 64 Chapter 4 A Charge Redistribution Based CIM Accelerator for CNNs 71 4.1 Introduction 71 4.2 Proposed Architecture 72 4.2.1 Low MAC Value Skipping technique [32] 76 4.3 Adopted Techniques of SAR ADC 77 4.3.1 Merged Capacitor Switching Method [39] 78 4.3.2 Direct Switching Technique [42] and compact combinational timing control [43] 80 4.4 Circuit Implementation 82 4.4.1 Peripheral Circuits of SRAM 82 4.4.2 Dynamic Comparator 85 4.4.3 Digital Control Logic Circuits 87 4.4.4 Capacitive DAC 88 Chapter 5 Simulation and Measurement Results 91 5.1 Layout and Chip Floor Plan 91 5.2 Simulation Results 93 5.3 Die Micrograph and Measurement Setup 97 5.4 Measurement Results 101 Chapter 6 Conclusion and Future Works 107 Bibliography 110

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