在邏輯元件的發展逼近物理極限的情形下，現有的半導體製程技術或架構已陸續面臨許多瓶頸。傳統製程技術的改良抑或是新製程架構的研發便成為延續摩爾定律的要務。有鑒於此，本論文旨在研究三項新興的半導體製程技術：中性束蝕刻、微波退火、及無晶種金屬化技術，並探討將它們整合應用至鰭式場效電晶體製程的可行性。
中性束蝕刻技術為一種將電漿離子中性化之後再與基材反應進行蝕刻之技術，預期可以避免傳統反應性離子蝕刻中因電荷累積造成的離子軌道偏移和氧化層缺陷，或是電漿中的紫外線輻射造成的表面缺陷等等。在本論文的第一部分，我們使用中性束來蝕刻高介電系數氧化層/金屬閘極電容，並以低中性化的條件模擬傳統反應性離子蝕刻，做為本研究的對照組。在電性量測的結果中我們發現，用中性束蝕刻的電容，較對照組之電容展現出較低的介面狀態密度、氧化層缺陷密度與漏電流密度。為了進一步確認電容側壁損傷的情形，我們設計了較小面積的電容並進行蝕刻。結果顯示以中性束蝕刻的小面積電容其漏電流密度並無顯著增加，反之對照組的漏電流則有顯著的上升。以上這些結果說明中性束蝕刻技術有效避免了傳統離子反應性蝕刻技術當中位於氧化層/矽基板介面以及元件側壁的電漿損傷，進而提升了高介電系數氧化層/金屬閘極的電性表現。
在本論文的第二部分，我們使用微波退火和傳統的快速熱退火分別對金氧半電容元件進行退火，並比較其電性表現的差異。微波退火因加熱的方式與傳統熱退火不同，將有機會達到較低的熱預算與較佳的熱均勻性。實驗結果顯示，經500˚C快速熱退火後的電容，雖然介面態密度及氧化層缺陷電荷密度皆有下降，但卻會因為金屬的擴散、介面氧化層增厚、還有氧化層結晶等問題而導致漏電流提升、崩潰電壓降低以及大量的平帶電壓偏移。在使用微波退火2700W的過程中量測到的試片溫度也為500˚C，但是此微波退火的試片得到了較低的有效氧化層厚度、缺陷密度、以及漏電流，同時沒有發現金屬擴散及介面氧化層增加的現象。這些結果顯示微波退火避免了傳統熱退火可能帶來的負面影響，在需要低熱預算的前段製程將是極具潛力的退火技術。
在第三部份我們結合了第一二部分的結論，實現了一個整合中性束蝕刻與微波退火製作的場效鰭式電晶體。使用中性束蝕刻矽鰭的元件當中，在寬度為40 nm與閘極長度100 nm的尺寸之下量測到的次臨限擺幅為89 mV/decade、工作電流3.85×10^-7 A/μm開關電流比10^6、汲極偏壓導致通道能障降低為72 mV/V、有效載子移動率502 cm^2V^-1^s-1，這些結果皆優於模擬反應性離子蝕刻的對照組。穿透式電子顯微鏡圖片的結果則顯示在對照組的蝕刻條件下在矽鰭表面會產生一層損傷層，為造成電性低落的主要原因。在比較不同元件尺寸的電性結果我們也發現，在不同閘極長度的元件之下，對照組之臨界電壓下降之情形較中性束蝕刻之元件嚴重；工作電流與鰭寬則呈現線性關係，說明經微波退火的源/汲極區電阻值極小，不足以影響工作電流。這些結果皆可作為中性束蝕刻和微波退火應用至先進半導體製程的展示和參考。
本論文的最後一部分討論了半導體製程的後段系統當中，使用合金材料作為無晶種阻障層的製程架構。我們利用過渡金屬的相互參雜來研究其抗腐蝕、抗擴散、濕潤、與直接電鍍的特性。實驗結果顯示在鈷鎢的合金系統當中，隨著鎢元素含量的上升，其失效溫度會上升，腐蝕電壓也會往惰性的方向偏移。但是在濕潤及電鍍的特性上，鎢含量上升卻使銅晶種的濕潤角度變小以及成核點數量降低。由以上結果可知，在合金阻障層當中其相對元素含量將會嚴重影響所需要的物理及電化學特性，而使我們必須在抗擴散、抗腐蝕以及濕潤與電鍍的能力上做權衡。在特定元素比例下，我們找到了單層的鈷鎢薄膜即可具有同等於現行氮化鉭薄膜之阻障能力、鉭薄膜的濕潤能力，且其銅電鍍的成核點密度符合次20奈米製程結點的要求，將有機會取代目前半導體金屬化技術當中擴散層/濕潤層/晶種層的製程架構。

When the feature size of logic devices is scaling down toward 10 nm and beyond, current manufacturing techniques are facing a variety of challenges due to higher processing requirement. Improvement on current techniques or development of novel technology thus becomes important to keep the Moore’s law alive. In this thesis, three kinds of novel fabrication techniques are studied- neutral beam etching (NBE), microwave annealing (MWA) and seedless metallization-, and the feasibility of these techniques to be adopted in the FinFET processes are also discussed.
In the first part of this study, NBE is applied to pattern high-k/metal gate MOS capacitors. Electrical characteristics of the capacitors by NBE and counterparts by a reactive-ion-etching-like (RIE-like) condition are studied, and a related plasma-induced damage model is also discussed. Results show that MOS capacitors etched by NBE demonstrated lower interface state density (Dit), oxide trap charges (Qot) and leakage current density. Furthermore, smaller capacitors etched by NBE did not lead to higher leakage current, indicating the sidewall damage was also suppressed. These results reveal that NBE is effective to prevent plasma-induced damages at the high-k/Si interface and on the sidewall and thus improve the electrical performance of the gate structure.
In the second part of the thesis, MWA over a wide range of power were performed on MOS capacitors. Capacitors with rapid thermal annealing (RTA) at 500 °C are also fabricated for comparison at the same wafer temperature measured during MWA at 2700 W. For microwave annealed capacitors, key parameters such as equivalent oxide thickness (EOT), Dit, Qot, leakage current density and breakdown voltage were all improved with increasing MWA power. For the capacitor with RTA at 500 °C, diffusion of Al into TiN and growth of the interfacial oxide layer are detected, leading to the shift in flat-band voltage (VFB) and increase in EOT, respectively. Without trade-off relationship between the electrical characteristics, MWA demonstrates great potential for front-end fabrication.
In the third part, FinFETs are realized by integrating NBE and MWA into the fabrication process. Sub-threshold swing of 89 mV/decade, Ion/Ioff of 10^6, DIBL of 72 mV/V and μeff of 502 cm^2V^-1s^-1 are obtained with Wfin/Lgate= 40/100 nm. These characteristics are superior by using neutral beam etching than by using RIE-like condition, and the Vt roll-off at reduced Lgate is also suppressed. A damaged layer at high-k/Si interface by RIE-like condition is observed in the TEM image, which can correspond to the degradation in electrical characteristics. Furthermore, the proportional scaling of Ion versus Wfin indicates negligible S/D resistance due to good activation by MWA. In short, functional FinFETs were fabricated by NBE and MWA for the first time, and these results pave ways for the techniques to be adopted in the advanced semiconductor processing.
In the final part of this thesis, tungsten-based seedless barriers with various chemical compositions for back-end application are investigated. For CoW alloys, higher W concentration is found to be beneficial for suppressing corrosion of CoW substrates and also improving the thermal stability. However, on the surface of Cu/CoW films with high W concentration, Cu agglomeration and pin-holes were found after annealing, indicating poor adhesion between Cu and high-W-content CoW alloys. These results indicate a trade-off relationship between barrier properties based on W concentration. CoW alloys with moderate W concentration around 50% are found to be a direct platable material which also demonstrates desirable adhesion and anti-diffusion characteristics for the sub-20 nm metallization process.

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Chapter 3
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Chapter 4
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Chapter 6
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