現在的電子產品，高速印刷電路板的密度及元件逐漸增加，頻率越高且工作電壓下降，使得電路中的電磁效應干擾造成訊號品質變差。電路工作由於快速切換，使得電路佈局層間寄生電容、電感效應，產生暫態切換雜訊，因而影響到電路的正常功能。在多層電路佈局上，電源雜訊就會藉由天線輻射之方式，將能量傳播及干擾其他產品，經由傳輸線及雜訊耦合。
本論文針對高速印刷電路板線路佈局，進行電源雜訊分析及修改,並彙整電磁輻射干擾的遠場及近場量測資料，使用電路佈局的模擬軟體，透過研究分析及量測驗證方式，以求高速數位訊號的完整性(signal integrity: SI)，並分析如何有效的運用線路佈局及電路設計，或是尋找出兩層印刷電路板線路佈局的法則，以降低電磁干擾輻射為目標，有效改善電路之電磁輻射干擾及其雜訊輻射。

This thesis presents a study of EMI effect on high-speed digital PCB layout. Analysis and debugging of PCB layout with power base or power integrity. To measure near field and far field of the EMI of differential pairs on high-speed PCB. Using IBIS model for signal integrity and EMI analysis in simulation tool. Simulation and measurement results are compared to establish a proper equivalent layout guideline or check list for high-speed digital circuit PCB, which will be useful for EMI design.

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