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研究生：	楊松輯 Yang, Song-Ji
論文名稱：	使用雙重取樣與依比例減少技巧管線式類比數位轉換器之設計 Design of Pipelined A/D Converter Using Double-sampling and Scaling Techniques
指導教授：	賴源泰 Lai, Yan-Tai
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	73
中文關鍵詞：	管線式類比數位轉換器、雙重取樣
外文關鍵詞：	Pipelined ADC, Double-sampling
相關次數：	點閱：63 下載：0
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近年來，在許多應用當中皆以數位訊號處理技術來處理傳輸的資訊，因此，在接收類比訊號及數位訊號處理系統之間，類比數位轉換器成為不可或缺的元件。由於製程技術的演進與可攜性系統的應用，在類比數位轉換器中，低電壓操作及低功率消耗的需求也變得越來越重要。因此，本論文針對管線式類比數位轉換器做設計，以高取樣頻率及低功率做為考量，引入雙重取樣技術來加倍取樣頻率而不使功率消耗倍增。此外，隨著管線式類比數位轉換器的每級規格限制越來越寬鬆，再針對每級需求做設計，可進一步減少管線式類比數位轉換器的整體功率消耗。
此類比數位轉換器藉由 TSMC 0.18um 1P6M CMOS 製程來實現一個使用雙重取樣技術之10位元100百萬赫茲管線式類比數位轉換器。所有類比電路皆以全差動輸入設計，輸入訊號為2伏特峰對峰值，操作電壓為1.8伏特。此管線式類比數位轉換器在時脈為50百萬赫茲，即取樣頻率為100百萬赫茲下，輸入訊號為1百萬赫茲弦波時，訊號對雜訊失真比(SNDR)為61.4dB。微分非線性誤差(DNL)為 +0.1/-0.3 LSB而積分非線性誤差(INL)為 +0.39/-0.38 LSB，其總功率消耗為41.4mW。

Recently, many of the applications utilize the digital signal processing (DSP) to deal with the transmitted of the information. Therefore, the analog-to-digital converter has become indispensable component between the received analog signal and DSP system. Due to the advance of deep submicron technology and the systems portability, the low power supply and the power consumption will become an increasingly important issue in the analog-to-digital converters. Therefore, the thesis focuses on the design of pipelined ADC architecture. Then, the aim of this thesis is to investigate the design techniques of ADCs for high sampling rate applications and low power dissipation. The double-sampling technique is introduced to double the sampling rate which is not consuming two times of power. Because of the required accuracy of pipelined ADC is relaxed in the following stages, the scaling technique is also applied to each stage. Thus, the total power consumption of the pipelined ADC is further reduced.
This 10-bit 100MS/s double-sampling pipelined ADC is implemented by TSMC 0.18um 1P6M CMOS process. All analog circuits are designed as fully differential with 2Vpp input signal and 1.8V power supply. The SNDR of pipelined ADC is 61.4dB for an input signal of 1MHz sine wave at a 50MHz clock rate i.e. a 100MS/s sampling rate. The DNL is about +0.1/-0.3 LSB, and INL is about +0.39/-0.38 LSB. The total power dissipation of pipelined ADC is about 41.4mW.

Table of Contents
Abstract	I
Acknowledgment	IV
Table of Contents	V
List of Figures	IX
List of Tables	XII

Chapter 1  Introduction	1
1  Motivation	1
2  Thesis Organization	3
Chapter 2  Fundamentals of ADC	4
1  Introduction	4
2  The Concept and Performance of A/D Converter	4
2.1  Aliasing Effect	5
2.2  Ideal A/D Converter	7
2.3  Quantization Error	8
3  A/D Converter Specification	10
3.1  Static Specification	10
3.1.1  Resolution	10
3.1.2  Accuracy	10
3.1.3  Offset error	11
3.1.4  Gain error	11
3.1.5  Integral nonlinearity	11
3.1.6  Differential nonlinearity	12
3.1.7  Monotonicity	13
3.1.8  Missing code	13
3.2  Dynamic Specification	13
3.2.1  Sampling rate and Conversion time	13
3.2.2  Signal-to-Noise Ratio (SNR)	14
3.2.3  Signal-to-Noise and Distortion Ratio (SNDR) 15
3.2.4  Spurious-Free Dynamic Ratio (SFDR)	15
3.2.5  Effective Number of Bits (ENOB)	15
3.2.6  Dynamic Range (DR)	16
4  Architectures of High Speed ADC Overview	17
4.1  Flash A/D Converter	18
4.2  Two-Step ADC	19
4.3  Pipelined ADC	20
4.4  Comparison and Summary of High Speed ADC	22
Chapter 3  The Analysis of Pipelined ADC with the
Double-Sampling Technique	24
1  Introduction	24
2  Conventional Pipelined ADC	25
3  Digital Error Correction Technique	27
4  Double Sampling Technique	30
4.1  Principle of Double Sampling	30
4.2  Non-idealities in the Double Sampling Circuit	31
4.2.1  Memory Effect	31
4.2.2  Offset Error	32
4.2.3  Gain Error	32
4.2.4  Timing Skew	32
5  Accuracy Requirement of Pipelined Stage	33
5.1  Capacitor Requirement	34
5.2  Op-Amp Requirement	35
Chapter 4  Design of Double-Sampling Pipelined
Analog-to-Digital Converter	38
1  Introduction	38
2  Operation Amplifier	39
2.1  Structure of the Amplifier	39
3  Front-End Sample and Hold Amplifier	44
3.1  MOS Switch	44
3.2  Sample and Hold Circuit with Double-Sampling	49
4  Sub-ADC	51
4.1  Dynamic Comparator	51
4.2  1.5-Bit Sub-ADC	54
4.3  2-Bit Flash ADC	55
5  Multiplying Digital-to-Analog converter (MDAC)	56
6  Clock Generator	58
7  Registers and Digital Error Correction	59
8  Scaling Technique	61
Chapter 5  Simulation Results of Pipelined
          Analog-to-Digital Converter	63
1  Experimental Results of Pipelined ADC	63
Chapter 6  Conclusion and Future Work	68
Reference	69

                                    

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